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| 型號(hào)： | AS8002-AQFP |
| 廠商： | ams |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CURRENT MEASURE SOLAR 16VQFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電源管理 |
| 輸入類型： | 模擬 |
| 輸出類型： | 數(shù)字 |
| 接口： | SPI 串行 |
| 電流 - 電源： | 5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AS8002-AQFPDKR |
www.austriamicrosystems.com/AS8002
Revision 1.1
21 - 24
AS8002
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
Table 30 provides examples of Gain selection of Channel 1 for different shunt resistors and maximum RMS currents.
8.1 Application Hints
Grounding and Layout. The analog and digital supplies of the AS8002 (AVDD, DVDD, AVSS, DVSS) are independent and separately
pinned out to minimize coupling between the analog and digital sections of the device. The printed circuit board (PCB) that houses the AS8002
should be designed such that the analog and digital sections are separated and confined to certain areas on the board. This design facilitates the
use of ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum etch technique is generally best. All VSS pins of the AS8002 should be sunk in the
ground plane. Digital and analog ground planes should be joined in only one spot. If the AS8002 is in a system where multiple devices require an
AVSS and DVSS connection, this connection should still be made at one point only; a star ground point that should be established as close as
possible to the ground pins on the AS8002.
Avoid running digital lines under the device as this couples noise into the chip. However, the analog ground plane should be allowed to run under
the AS8002 to avoid noise coupling. The power supply lines to the AS8002 should use as large trace width as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Likewise, the positive supply pins AVDD and DVDD should be connected only at one common star point close the output of the power supply.
For best performance of the analog blocks of the AS8002, it is important to have a clean, noise-free supply voltage at AVDD.
To avoid radiating noise to other sections of the board, fast switching signals, such as clocks, should be shielded with digital ground, and clock
signals should never run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the
board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is the best method but is not always
possible with a double sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on
the opposite side.
Good decoupling is also important. All analog supplies should be decoupled with 10F ceramic capacitors in parallel with 0.1F capacitors to
GND. Refer to Typical Application Circuit (page 9). To achieve the best results from these decoupling components, they must be placed as close
as possible to the device The 0.1F capacitors should have low effective series resistance (ESR) and low effective series inductance (ESI), such
as common ceramic types or surface-mount types. These low ESR and ESI capacitors provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic switching.
Table 30. Gain Selection
Shunt Resistor Value
Sensing RMS Current (A)
Recommended Linear Gain for Channel 1 for
ADC to work in 80% of dynamic range
7.5 m
Ω
1.5
Gain1 = 64
10 m
Ω
1.5
Gain1 = 48
5 m
Ω
3
Gain1 = 48
7.5 m
Ω
3
Gain1 = 32
10 m
Ω
3
Gain1 = 24
5 m
Ω
6
Gain1 = 24
7.5 m
Ω
6
Gain1 = 16
10 m
Ω
6
Gain1 = 12
ams
AG
Technical
content
still
valid
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