參數(shù)資料
型號(hào): AS7C33512NTD18A-166BC
廠商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): SRAM
英文描述: 512K X 18 ZBT SRAM, 9 ns, PBGA119
封裝: 14 X 20 MM, BGA-119
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 299K
代理商: AS7C33512NTD18A-166BC
AS7C33512NTD16A
AS7C33512NTD18A
3/11/02;
v.1.8H
Alliance Semiconductor
10 of 12
AC test conditions
Z0 = 50
DOUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
for 2.5V I/O
Thevenin equivalent:
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This paracmeter measured with output load conditon in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured HIGH above VIH and tCL measured as LOW below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/W, BW[a:d]
.
8) Chip select refers to CE0, CE1, CE2.
353
/1538
5 pF*
319
/1667
DOUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
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