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參數(shù)資料
| 型號： | AS7C1026A-12BC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V/3.3V 64K X 16 CMOS SRAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 12 ns, PBGA48 |
| 封裝： | 6 X 8 MM, BGA-48 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 148K |
| 代理商： | AS7C1026A-12BC |
AS7C1026A
AS7C31026A
2/6/01
Alliance Semiconductor
P. 6 of 9
Data retention characteristics (over the operating range)
Parameter
Data retention waveform
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C=30pF, except all high Z and low Z parameters where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A, B, and C.
These parameters are specified with C
L
= 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Symbol
Test conditions
Min
Max
Unit
V
CC
for data retention
Data retention current
V
DR
I
CCDR
t
CDR
t
R
|I
LI
|
V
CC
= 2.0V
CE
≥
V
CC
–0.2V
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
2.0
–
V
–
1
ma
Chip deselect to data retention time
0
–
ns
Operation recovery time
t
RC
–
–
ns
μ
A
Input leakage current
1
V
CC
CE
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255W
C(14)
320W
GND
+3.3V
Figure C: 3.3V Output load
168W
Thevenin Equivalent:
D
OUT
+1.728V (5V and 3.3V)
255W
C(14)
480W
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
D
OUT
D
OUT
– Output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V
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| AS7C1026A-12JC | 5V/3.3V 64K X 16 CMOS SRAM |
| AS7C1026A-12JI | 5V/3.3V 64K X 16 CMOS SRAM |
| AS7C1026A-12TC | 5V/3.3V 64K X 16 CMOS SRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1026A-12JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 64K X 16 CMOS SRAM |
| AS7C1026A-12JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 64K X 16 CMOS SRAM |
| AS7C1026A-12TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 64K X 16 CMOS SRAM |
| AS7C1026A-15 | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 64K X 16 CMOS SRAM |
| AS7C1026A-15BC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 64K X 16 CMOS SRAM |
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