參數(shù)資料
型號: AS5LC1008DJ-15/IT
廠商: AUSTIN SEMICONDUCTOR INC
元件分類: SRAM
英文描述: 128K x 8 SRAM High-Speed CMOS SRAM with 3.3V Revolutionary Pinout
中文描述: 128K X 8 STANDARD SRAM, 15 ns, PDSO32
封裝: 0.400 INCH, PLASTIC, SOJ-32
文件頁數(shù): 7/10頁
文件大?。?/td> 521K
代理商: AS5LC1008DJ-15/IT
SRAM
AS5LC1008
AS5LC1008
Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
Austin Semiconductor, Inc.
WRITE CYCLE SWITCHING CHARACTERISTICS1,3
(-55oC < T
A
< +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
WRITE CYCLE #11,2 (CE\ Controlled, OE\ = HIGH or LOW)
NOTES:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in
Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
-10
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX UNITS
Write Cycle Time
tWC
10
---
12
---
15
---
20
---
ns
CE\ to Write End
tSCE
7
---
8
---
9
---
10
---
ns
Address Setup Time to Write End
tAW
8
---
9
---
10
---
12
---
ns
Address Hold from Write End
tHA
0
---
0
---
0
---
0
---
ns
Address Setup Time
tSA
0
---
0
---
0
---
0
---
ns
WE\ Pulse Width (OE\ HIGH)
tPWE1
1
7
---
8
---
9
---
10
---
ns
WE\ Pulse Width (OE\ LOW)
tPWE2
2
10
---
12
---
12
---
15
---
ns
Data Setup to Write End
tSD
5
---
6
---
7
---
8
---
ns
Data Hold to Write End
tHD
0
---
0
---
0
---
0
---
ns
WE\ LOW to High-Z Output
tHZWE
2
---
5
---
6
---
7
---
8
ns
WE\ HIGH to Low-Z Output
tLZWE
2
---
2
---
2
---
2
---
ns
-20
-12
-15
相關(guān)PDF資料
PDF描述
AS5LC1008DJ-15/XT High-Speed CMOS SRAM with 3.3V Revolutionary Pinout
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