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參數(shù)資料
| 型號： | AS4C1M16F5-60JC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5V 1M X 16 CMOS DRAM |
| 中文描述： | 5V的100萬× 16的CMOS內(nèi)存 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 485K |
| 代理商： | AS4C1M16F5-60JC |
AS4C1M16F5
4/11/01; v.0.9.1
Alliance Semiconductor
P. 2 of 21
Functional description
The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as
1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design
techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The
Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia
and router switch applications.
The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page)
can be executed at very high speed (15 ns from
XCAS
)by toggling column addresses within that row. Row and column
addresses are alternately latched into input buffers using the falling edge of
RAS
and
xCAS
inputs respectively. Also,
RAS
is used
to make the column address latch transparent, enabling application of column addresses prior to
xCAS
assertion. The
AS4C1M16F5 provides dual
UCAS
and
LCAS
for independent byte control of read and write access.
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:
RAS
-only refresh:
RAS
is asserted while
xCAS
is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.
Hidden refresh:
xCAS
is held low while
RAS
is toggled. Outputs remain low impedence with previous valid data.
CAS
-before-
RAS
refresh (CBR): At least one
xCAS
is asserted prior to
RAS
. Refresh address is generated internally.
Outputs are high-impedence (
OE
and
WE
are don't care).
Normal read or write cycles refresh the row being accessed.
The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates
with a single power supply of 5V ± 0.5V The device provides TTL compatible inputs and outputs.
Logic block diagram
Recommended operating conditions
Parameter
V
IL
min -3.0V for pulse widths less than 5 ns.
Recommended operating conditions apply throughout this document unlesss otherwise specified.
Symbol
Min
Nominal
Max
Unit
Supply voltage
AS4C1M16F5
V
CC
GND
4.5
5.0
5.5
V
0.0
0.0
0.0
V
Input voltage
AS4C1M16F5
V
IH
V
IL
2.4
–0.5
–
V
CC
0.8
V
–
V
Ambient operating temperature
Commercial
T
A
0
–
70
°C
Industrial
-40
–
85
RAS clock
generator
R
c
1024 × 1024 × 16
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
V
CC
GND
A
R
Column decoder
Substrate bias
generator
Data
DQ
buffers
OE
RAS
UCAS
LCAS
WE clock
generator
WE
DQ1 to DQ16
CAS clock
generator
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS4C1M16F5-60JI | 5V 1M X 16 CMOS DRAM |
| AS4C1M16F5-60TC | 5V 1M X 16 CMOS DRAM |
| AS4C1M16F5-60TI | 5V 1M X 16 CMOS DRAM |
| ASG402 | DC-3000 MHz SiGe HBT Amplifier |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4C1M16F5-60JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V 1M X 16 CMOS DRAM |
| AS4C1M16F5-60TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V 1M X 16 CMOS DRAM |
| AS4C1M16F5-60TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V 1M X 16 CMOS DRAM |
| AS4C1M16S-6TCN | 功能描述:IC SDRAM 16MBIT 166MHZ 50TSOP 制造商:alliance memory, inc. 系列:- 包裝:托盤 零件狀態(tài):在售 存儲器類型:易失 存儲器格式:DRAM 技術(shù):SDRAM 存儲容量:16Mb （1M x 16） 時鐘頻率:166MHz 寫周期時間 - 字，頁:2ns 訪問時間:5.4ns 存儲器接口:并聯(lián) 電壓 - 電源:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C（TA） 安裝類型:表面貼裝 封裝/外殼:50-TSOP（0.400"，10.16mm 寬） 供應(yīng)商器件封裝:50-TSOP II 標(biāo)準(zhǔn)包裝:117 |
| AS4C1M16S-6TCNTR | 功能描述:IC SDRAM 16MBIT 166MHZ 50TSOP 制造商:alliance memory, inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 存儲器類型:易失 存儲器格式:DRAM 技術(shù):SDRAM 存儲容量:16Mb （1M x 16） 時鐘頻率:166MHz 寫周期時間 - 字，頁:2ns 訪問時間:5.4ns 存儲器接口:并聯(lián) 電壓 - 電源:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C（TA） 安裝類型:表面貼裝 封裝/外殼:50-TSOP（0.400"，10.16mm 寬） 供應(yīng)商器件封裝:50-TSOP II 標(biāo)準(zhǔn)包裝:1,000 |
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