參數(shù)資料
型號(hào)： AR-20441-12
廠商： Conexant Systems, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:12; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:28; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:28-18 RoHS Compliant: No
中文描述： AccessRunner ADSL調(diào)制解調(diào)器的PCI設(shè)備的應(yīng)用設(shè)置
文件頁(yè)數(shù)： 8/24頁(yè)
文件大小： 159K
代理商： AR-20441-12
AccessRunner
Controller-less ADSL Modem Device Set for PCI Applications
8
Conexant
Proprietary Information
Doc. No. 100394B
October 19, 1999
Pin Name
I/O
1
Description
AFE_WAKEUP
I (S)
DSL Power Management Wakeup Signal from AFE
SERIAL EEPROM
EEPROM_CS
O
EEPROM Chip Select
EEPROM_CLK
O
EEPROM Clock
EEPROM_DIN
I
EEPROM Data Input
EEPROM_DOUT
O
EEPROM Data Output
PCI POWER MANAGEMENT
PCI_VAUXDET
I (PD,S)
Vaux Detect
PCI_VPCIDET
I (PD,S)
Vpci Detect
PCI_VAUXEN#
O
Vaux Enable
PCI_VPCIEN#
O
Vpci Enable
PCI_VPCIPREFER
I
This pin is used to determine whether Vpci or Vaux is the preferred power supply.
1=Vpci preferred, 0=Vaux preferred
MISCELLANEOUS
GPIO[1:0]
I/O (PU,S)
General Purpose Schmitt Input/Output
GPIO[2:5], GPIO[8]
I/O (PU)
General Purpose Input/Output
GPIO[6]
I/O
General Purpose Input/Output (also used for active low reset)
GPIO[7]
I/O
General Purpose Input/Output (also used for active high reset)
TDI_GPIO[9]
I/O (PU)
JTAG test data input OR general purpose input/output. Function of this pin is
dependant upon value of JTAGEN bit. When operating in JTAG mode this signal
contains serial data that is shifted in on the rising edge of TCK.
TMS_GPIO[10]
I/O (PU)
JTAG test mode select OR general purpose input/output.
Function of this pin is dependant upon value of JTAGEN bit. When operating in JTAG
mode this siganl controls the operation of the TAP controller.
TRSTN_GPIO[11]
I/O (PU)
JTAG reset OR general purpose input/output.
Function of this pin is dependant upon value of JTAGEN bit. When operating in JTAG
mode, a high to low transition on this signal forces the TAP controller into a logic reset
state.
TCK
I
JTAG clock.
TDO
O
JTAG data output. This pin generates serial data that is shifted out on the falling edge
of TCK..
GPIN0
I (S)
General purpose schmitt input (modem ring detect)
GPIN1
I (PU,S)
General purpose schmitt input (modem offhook)
SCANEN
I (PD)
Scan chain enable. Used to shift data in and out of the scan chain.
SCANMODE
I (PD)
Scan mode enable pin. When tied high it will put the device into scan test mode.
REFCLK
I
35.328 MHz reference clock used to create the internal 53 MHz system clock
POWER AND GROUND
VDD
3.3V Power
GND
Ground
VGG1
I/O Clamp Power Supply for PCI Signalling Environment (connect to VIO pin of PCI
Bus)
VGG2
I/O Clamp Power Supply for Backend (connect to 3.3 volt supply)
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