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參數(shù)資料
| 型號： | APR6008 |
| 廠商： | Aplus Integrated Circuits Inc. |
| 英文描述： | LJT 43C 23#20 20#16 PN WALL RE |
| 中文描述： | 錄音 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 2267K |
| 代理商： | APR6008 |
APR6008
Page 16
Voice Recording & Playback Device
Revision 2.1
Pin Descriptions
Table three shows pin descriptions for the APR6008 device.
All pins are listed in numerical order with the exception of
VCC, VSS and NC pins which are listed at the end of the
table.
Table 3
APR6008 28 Pin Number & Description
Pin Name
Pin No.
28 pin
SOP
Pin No.
28 pin
DIP
Pad No. (Die)
Reference Figure
18
Functionality
SAC
24
24
27
Sector Address Control Output:
This active low output indicates when the
device is nearing the end of the current segment.
/INT
25
25
28
Interrupt Output:
This active low open drain output goes low whenever the
device reaches the end of a message or the device overflows. When connected
to the interrupt input of the host microcontroller this output can be used to imple-
ment powerful message management options.
EXTCLK
26
26
29
External Clock Input:
This input can be used to feed the device an external
sample clock instead of using the internal sampling clock. This pin should be con-
nected to VSSA when not in use.
SCLK
28
28
33
SPI Clock Input:
Data is clocked into the device through the DI pin upon the ris-
ing edge of this clock. Data is clocked out of the part through the DO pin on the
falling edge.
/CS
1
1
2
Chip Select Input:
This active low input selects the device as the currently active
slave on the SPI interface. When this pin is high the device tri-states the DO pin
and ignores data on the DI pin.
DI
2
2
3
Data Input:
The DI input pin receives the digital data input from the SPI bus.
Data is clocked on the rising edge of the SCLK input.
DO
3
3
4
Data Output:
Data is available after the falling edge of the SCLK input.
ANAOUT-
8
8
9
Negative Audio Output:
This is the negative audio output for playback of pre-
recorded messages. This output is usually fed to the negative input of a differen-
tial input power amplifier. The power amplifier drives an external speaker.
ANAOUT+
9
9
10
Positive Audio Output:
This is the positive audio output for playback of pre-
recorded messages. This output is usually fed to the positive input of a differential
input power amplifier. The power amplifier drives an external speaker.
/RESET
11
11
11
Reset Input:
This active low input clears all internal address registers and
restores the device to its power up defaults.
AUDOUT
13
13
15
Single Ended Audio Output:
This is the audio output for playback of pre-
recorded messages. This output is usually fed to the input of a power amplifier for
driving an external speaker.
SQLCAP
14
14
16
Squelch Capacitor I/O:
This pin controls the attack time of the squelch circuitry.
Connect his pin to GND through a 1.0 uf capacitor to enable the squelch feature.
The capacitor’s time constant will affect how quickly the squelch circuitry reacts.
Connect this pin to VCCA to disable the squelch feature.
/SQL
15
15
17
Squelch Output:
This active low output indicates when the internal squelch cir-
cuitry has activated. This signal can be used to automatically squelch the external
power amplifier. Squelching the external power amplifier can result in an even
greater reduction of background noise.
ANAIN-
16
16
18
Inverting Analog Input:
This input is the inverting input for the analog signal that
the user wishes to record. When the device is used in a differential input configu-
ration this pin should receive a 16 mV peak to peak input coupled through a
0.1uF capacitor. When the device is used in a single ended input configuration
this input should be tied to VSSA through a 0.1 uF capacitor.
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