參數(shù)資料
型號(hào): APE8957MP
廠商: ADVANCED POWER ELECTRONICS CORP
元件分類: 可調(diào)正電壓?jiǎn)温份敵鯨DO穩(wěn)壓器
英文描述: ADJUSTABLE POSITIVE LDO REGULATOR, PDSO8
封裝: HALOGEN FREE AND ROHS COMPLIANT, ESOP-8
文件頁數(shù): 4/6頁
文件大?。?/td> 322K
代理商: APE8957MP
Advanced Power
Electronics Corp.
APE895
7
FUNCTION PIN DESCRIPTION
FB
VOUT = 0.8 x (1 + R1/R2)
VIN and Exposed Pad
Main supply input pins for power conversions. The exposed pad provides a very
low
impedance input path for the main supply voltage. Please tie the exposed pad and
VIN Pin
(Pin 5) together to reduce the dropout voltage. The voltage at this pin is
monitored for
Power-On Reset purpose.
VCNTL
POK
EN
VOUT
FUNCTION DESCRIPTION
Power-On-Reset
Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins
to prevent wrong logic controls. The POR function initiates a soft-start process after the
two supply voltages exceed their rising POR threshold voltages during powering on. The
POR function also pulls low the POK pin regardless the output voltage when the VCNTL
voltage falls below it’s falling POR threshold.
Internal Soft-Start
An internal soft-start function controls rise rate of the output voltage to limit the
current surge at start-up. The typical soft-start interval is about 2ms.
Current Limit
The APE8957 monitors the current via the output NMOS and limits the maximum
current to prevent load and APE8957 from damage during overload or short circuit
4
Connecting this pin to an external resistor divider receives the feedback voltage
of
the regulator. The output voltage set by the resistor divider is determined by:
Where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected
from FB to GND. A bypass capacitor may be connected with R1 in parallel to improve load
transient response. The recommended R2 and R1 are in the range of 1k~100kohm.
Power input pin of the control circuitry. Connecting this pin to a +5V(recommended)
supply voltage provides the bias for the control circuitry. The voltage at this pin is
monitored
for Power-On Reset purpose.
Power-OK signal output pin. This pin is an open-drain output used to indicate status
of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage
is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold,
indicating the output is not OK.
Enable control pin. Pulling and holding this pin below 0.4V shuts down the output.
When re-enabled, the IC undergoes a new soft-start cycle. Left this pin open, an internal
current source 10uA pulls this pin up to VCNTL voltage, enabling the regulator.
Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It's
necessary to connect an output capacitor with this pin for closed-loop compensation and
improving transient responses.
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