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參數(shù)資料
| 型號(hào)： | APC5830 |
| 廠商： | Aplus Integrated Circuits Inc. |
| 英文描述： | APC5830 DE-COMPRESSION VOICE IC |
| 中文描述： | APC5830德壓縮語(yǔ)音IC |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 252K |
| 代理商： | APC5830 |
APLUS INTEGRATED CIRCUITS INC.
APC5830
www.aplusinc.com.tw
TEL : 886-2-2782-9266
z
3FF6 :
P
ORT
_
C
[7..0]
DATA REGISTER
. R
EAD AND WRITE
.
z
3FF7
: P
ORT
_
C
[15..8]
DATA REGISTER
. R
EAD AND WRITE
.
z
3FF8
: P
ORT
_
C
[7..0]
DIRECTION REGISTER
. W
RITE ONLY
.
A
N
‘1’
IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT
_
C TO BE OUTPUT
.
T
HE DEFAULT VALUE FOR EACH BIT IS ZERO
.
z
3FF9
: P
ORT
_
C
[15..8]
DIRECTION REGISTER
. W
RITE ONLY
.
A
N
‘1’
IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT
_
C TO BE OUTPUT
.
T
HE DEFAULT VALUE FOR EACH BIT IS ZERO
.
z
3FFA
:ADC
REGISTER
. R
EAD ONLY
.
W
HEN THE TIMER B
NMI
OCCURS
,
THE
A/D
CONVERSION PROCESS STARTS AND THE
S/H
CIRCUIT STOP SAMPLING AND BEGIN HOLDING IT UNTIL THE
ADC
PROCESS IS FINISHED
.
T
HE
ADC
INT WILL GENERATE WHEN
ADC
PROCESS IS FINISHED
.
z
3FFB,3FFC :
….
NO USE
z
3FFD :
……
NO USE
z
3FFE:
V
OICE CHANNEL
1
LOW BYTE AND SYSTEM CONTROL
3. W
RITE ONLY
.
3FFE
0
1
BIT - 0
S
EPARATE MODE FOR
DAC
OUTPUT
(
DEFAULT
)
S
EPARATE MODE FOR
PWM
OUTPUT
(
DEFAULT
)
M
IX MODE FOR
DAC
OUTPUT
.
BIT - 1
M
IX MODE FOR
PWM
OUTPUT
BIT - 2
BIT - 3
BIT – 7 ~ 4
NO USE
(
MUST
0)
NO USE
(
MUST
0)
VOICE CHANNEL
1
LOW NIBBLE BYTE
.
z
3FFF
: V
OICE CHANNEL
1
HIGH BYTE
. W
RITE ONLY
.
T
HE RESOLUTION OF VOICE CHANNEL
1
IS
12
BITS
($3FFF,$3FFE
BIT
7_4). T
HIS REGISTER
WILL BE TRANSFERRED TO
PWM
PORT WHILE TIMER
_
B
NMI
HAPPEN IN SEPARATE MODE
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| APC5860 | 制造商:APLUS 制造商全稱:APLUS 功能描述:APC5860 DE-COMPRESSION VOICE IC |
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