ProASICPLUS Flash Family FPGAs v5.9 2-47 Table 2-37 Worst-Case Military " />
參數(shù)資料
型號: APA750-PQG208I
廠商: Microsemi SoC
文件頁數(shù): 132/178頁
文件大小: 0K
描述: IC FPGA PROASIC+ 750K 208-PQFP
標準包裝: 24
系列: ProASICPLUS
RAM 位總計: 147456
輸入/輸出數(shù): 158
門數(shù): 750000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
ProASICPLUS Flash Family FPGAs
v5.9
2-47
Table 2-37 Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Macro Type
Description
Max. tINYH
1
Max. tINYL
2
Units
Std.
IB33
3.3 V, CMOS Input Levels3, No Pull-up Resistor
0.5
0.6
ns
IB33S
3.3 V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger
0.6
0.8
ns
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP =2.3 V for delays.
Table 2-38 Worst-Case Military Conditions
VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Macro Type
Description
Max. tINYH
1
Max. tINYL
2
Units
Std.
IB25LP
2.5 V, CMOS Input Levels3, Low Power
0.9
0.7
ns
IB25LPS
2.5 V, CMOS Input Levels3, Low Power, Schmitt Trigger
0.8
1.0
ns
Notes:
1. tINYH = Input Pad-to-Y High
2. tINYL = Input Pad-to-Y Low
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP =2.3 V for delays.
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