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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA600-FG484A
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 114/178闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA PROASIC+ 600K 484-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 129024
杓稿叆/杓稿嚭鏁�(sh霉)锛� 370
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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ProASICPLUS Flash Family FPGAs
2- 30
v5.9
The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.
This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as
follows:
Pclock
=>
Pclock = (P1 + (P2*R) - (P7*R
2)) * Fs = 121.5 mW
Pstorage
=>
Pstorage = P5 * ms * Fs = 147.8 mW
Plogic
=>
Plogic = 0 mW
Poutputs
=>
Poutputs = (P4 + (Cload * VDDP
2)) * p * Fp = 91.4 mW
Pinputs
=>
Pinputs = P8 * q * Fq = 0.3 mW
Pmemory
=>
Pmemory = 0 mW
Pac
=>
361 mW
Ptotal
Pdc + Pac = 374 mW (typical)
Fs
= 10 MHz
R
= 13,440
ms
= 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)
mc
= 0 (no logic tiles in this shift register)
Cload
=
40 pF
VDDP
=
3.3 V
p=
24
Fp
=
5 MHz
q=
1
Fq
=
10 MHz
Nmemory
=
0 (no RAM/FIFO blocks in this shift register)
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