ProASICPLUS Flash Family FPGAs 2- 50 v5.9 Predicted Global Routing Delay Global " />
參數(shù)資料
型號: APA600-CQ208B
廠商: Microsemi SoC
文件頁數(shù): 136/178頁
文件大小: 0K
描述: IC FPGA PROASIC+ 600K 208-CQFP
標準包裝: 1
系列: ProASICPLUS
RAM 位總計: 129024
輸入/輸出數(shù): 158
門數(shù): 600000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
封裝/外殼: 208-BFCQFP,帶拉桿
供應商設備封裝: 208-CQFP(75x75)
ProASICPLUS Flash Family FPGAs
2- 50
v5.9
Predicted Global Routing Delay
Global Routing Skew
Table 2-43 Worst-Case Commercial Conditions1
VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C
Parameter
Description
Max.
Units
Std.
tRCKH
Input Low to High2
1.1
ns
tRCKL
Input High to Low2
1.0
ns
tRCKH
Input Low to High3
0.8
ns
tRCKL
Input High to Low3
0.8
ns
Notes:
1. The timing delay difference between tile locations is less than 15 ps.
2. Highly loaded row 50%.
3. Minimally loaded row.
Table 2-44 Worst-Case Military Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Parameter
Description
Max.
Units
tRCKH
Input Low to High (high loaded row of 50%)
1.1
ns
tRCKL
Input High to Low (high loaded row of 50%)
1.0
ns
tRCKH
Input Low to High (minimally loaded row)
0.8
ns
tRCKL
Input High to Low (minimally loaded row)
0.8
ns
Note: * The timing delay difference between tile locations is less than 15 ps.
Table 2-45 Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C
Parameter
Description
Max.
Units
Std.
tRCKSWH
Maximum Skew Low to High
270
ps
tRCKSHH
Maximum Skew High to Low
270
ps
Table 2-46 Worst-Case Commercial Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883
Parameter
Description
Max.
Units
tRCKSWH
Maximum Skew Low to High
270
ps
tRCKSHH
Maximum Skew High to Low
270
ps
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