鍨嬭櫉(h脿o)锛� | APA450-BGG456 |
寤犲晢锛� | Microsemi SoC |
鏂囦欢闋佹暩(sh霉)锛� | 54/178闋� |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC FPGA PROASIC+ 450K 456-PBGA |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 24 |
绯诲垪锛� | ProASICPLUS |
RAM 浣嶇附瑷�(j矛)锛� | 110592 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 344 |
闁€鏁�(sh霉)锛� | 450000 |
闆绘簮闆诲锛� | 2.3 V ~ 2.7 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 70°C |
灏佽/澶栨锛� | 456-BBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 456-PBGA锛�35x35锛� |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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RMC50DRXS-S734 | CONN EDGECARD 100PS DIP .100 SLD |
GSC65DRYS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
GMC65DRYS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
EPF10K30RI240-4 | IC FLEX 10K FPGA 30K 240-RQFP |
GMC60DRXI-S734 | CONN EDGECARD 120PS DIP .100 SLD |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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APA450-BGG456I | 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 450K 456-PBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASICPLUS 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛� |
APA450-BGGB | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
APA450-BGGES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
APA450-BGGI | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |
APA450-BGGM | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs |