ProASICPLUS Flash Family FPGAs v5.9 2-23 Note: Each RAM block contains a mult" />
參數(shù)資料
型號： APA300-CQ208B
廠商： Microsemi SoC
文件頁數(shù)： 106/178頁
文件大小： 0K
描述： IC FPGA PROASIC+ 300K 208-CQFP
標準包裝： 1
系列： ProASICPLUS
RAM 位總計： 73728
輸入/輸出數(shù)： 158
門數(shù)： 300000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
封裝/外殼： 208-BFCQFP，帶拉桿
供應(yīng)商設(shè)備封裝： 208-CQFP（75x75）
ProASICPLUS Flash Family FPGAs
v5.9
2-23
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 2-19 Basic FIFO Block Diagrams
Table 2-15 Memory Block FIFO Interface Signals
FIFO Signal
Bits
In/Out
Description
WCLKS
1
In
Write clock used for synchronization on write side
RCLKS
1
In
Read clock used for synchronization on read side
LEVEL <0:7>
8
In
Direct configuration implements static flag logic
RBLKB
1
In
Read block select (active Low)
RDB
1
In
Read pulse (active Low)
RESET
1
In
Reset for FIFO pointers (active Low)
WBLKB
1
In
Write block select (active Low)
DI<0:8>
9
In
Input data bits <0:8>, <8> will be generated parity if PARGEN is true
WRB
1
In
Write pulse (active Low)
FULL, EMPTY
2
Out
FIFO flags. FULL prevents write and EMPTY prevents read
EQTH, GEQTH
2
Out
EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO<0:8>
9
Out
Output data bits <0:8>. <8> will be parity output if PARGEN is true.
RPE
1
Out
Read parity error (active High)
WPE
1
Out
Write parity error (active High)
LGDEP <0:2>
3
In
Configures DEPTH of the FIFO to 2 (LGDEP+1)
PARODD
1
In
Parity generation/detect – Even when Low, odd when High
FIFO
(256x9)
LEVEL<0:7>
DO <0:8>
DI<0:8>
WRB
RDB
WBLKB
RBLKB
RPE
PARODD
WPE
LGDEP<0:2>
FULL
EMPTY
EQTH
GEQTH
WCLKS
RCLKS
RESET
RPE
WPE
FULL
EMPTY
EQTH
GEQTH
DO <0:8>
RPE
WPE
FULL
EMPTY
EQTH
GEQTH
DI <0:8>
DO <0:8>
LEVEL <0:7>
WRB
RDB
WBLKB
RBLKB
RPE
PARODD
WPE
LGDEP<0:2>
DI <0:8>
LEVEL <0:7>
WRB
RDB
WBLKB
RBLKB
PARODD
LGDEP<0:2>
FULL
EMPTY
EQTH
GEQTH
RCLKS
RESET
LEVEL<0:7>
DI<0:8>
WRB
RDB
WBLKB
RBLKB
PARODD
LGDEP<0:2>
WCLKS
DO <0:8>
FIFO
(256x9)
FIFO
(256x9)
FIFO
(256x9)
Sync Write
and
Sync Read
Ports
Sync Write
and
Async Read
Ports
Async Write
and
Sync Read
Ports
Async Write
and
Async Read
Ports
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA300-CQ208M 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 208CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 300K 208CQFP
APA300-CQ352B 功能描述:IC FPGA PROASIC+ 300K 352-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
APA300-CQ352M 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 352CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 300K 352CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 248 I/O 352CQFP
APA300-CQB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA300-CQES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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