ProASICPLUS Flash Family FPGAs 2- 42 v5.9 Tristate Buffer Delays Figure 2-23 " />
鍙冩暩璩囨枡
鍨嬭櫉锛� APA150-TQ100
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩锛� 127/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 150K 100-TQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁革細 66
闁€鏁革細 150000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 100-LQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-TQFP锛�14x14锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�鐣跺墠绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�
ProASICPLUS Flash Family FPGAs
2- 42
v5.9
Tristate Buffer Delays
Figure 2-23 Tristate Buffer Delays
Table 2-27 Worst-Case Commercial Conditions
VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70掳C
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Max.
tENZH
3
Max.
tENZL
4
Units
Std.
OTB33PH
3.3 V, PCI Output Current, High Slew Rate
2.0
2.2
2.0
ns
OTB33PN
3.3 V, High Output Current, Nominal Slew Rate
2.2
2.9
2.4
2.1
ns
OTB33PL
3.3 V, High Output Current, Low Slew Rate
2.5
3.2
2.7
2.8
ns
OTB33LH
3.3 V, Low Output Current, High Slew Rate
2.6
4.0
2.8
3.0
ns
OTB33LN
3.3 V, Low Output Current, Nominal Slew Rate
2.9
4.3
3.2
4.1
ns
OTB33LL
3.3 V, Low Output Current, Low Slew Rate
3.0
5.6
3.3
5.5
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. tENZH = Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
Table 2-28 Worst-Case Commercial Conditions
VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70掳C
Macro Type
Description
Max.
tDLH
1
Max.
tDHL
2
Max.
tENZH
3
Max.
tENZL
4
Units
Std.
OTB25LPHH
2.5 V, Low Power, High Output Current, High Slew Rate5
2.0
2.1
2.3
2.0
ns
OTB25LPHN
2.5 V, Low Power, High Output Current, Nominal Slew Rate5
2.4
3.0
2.7
2.1
ns
OTB25LPHL
2.5 V, Low Power, High Output Current, Low Slew Rate5
2.9
3.2
3.1
2.7
ns
OTB25LPLH
2.5 V, Low Power, Low Output Current, High Slew Rate5
2.7
4.6
3.0
2.6
ns
OTB25LPLN
2.5 V, Low Power, Low Output Current, Nominal Slew Rate5
3.5
4.2
3.8
ns
OTB25LPLL
2.5 V, Low Power, Low Output Current, Low Slew Rate5
4.0
5.3
4.2
5.1
ns
Notes:
1. tDLH = Data-to-Pad High
2. tDHL = Data-to-Pad Low
3. tENZH = Enable-to-Pad, Z to High
4. tENZL = Enable-to-Pad, Z to Low
5. Low power I/O work with VDDP = 2.5 V 卤10% only. VDDP = 2.3 V for delays.
PAD
A
OTBx
A
50%
PAD
VOL
VOH
50%
t
DLH
50%
t
DHL
EN
50%
PAD
VOL
50%
t
ENZL
50%
10%
EN
50%
PAD
GND
V
OH
50%
t
ENZH
50%
90%
VDDP
35 pF
EN
鐩搁棞PDF璩囨枡
PDF鎻忚堪
IDT71024S20YGI8 IC SRAM 1MBIT 20NS 32SOJ
APA150-TQG100 IC FPGA PROASIC+ 150K 100-TQFP
A3P600-FG484 IC FPGA 1KB FLASH 600K 484-FBGA
M1A3P600-FGG484 IC FPGA 1KB FLASH 600K 484-FBGA
M1A3P600-FG484 IC FPGA 1KB FLASH 600K 484-FBGA
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�
鍙冩暩鎻忚堪
APA150-TQ100A 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 150K 100-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASICPLUS 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�:- 閭忚集鍏冧欢/鍠厓鏁�:- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�:157 闁€鏁�:250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
APA150-TQ100I 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 150K 100-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASICPLUS 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�:- 閭忚集鍏冧欢/鍠厓鏁�:- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�:157 闁€鏁�:250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
APA150-TQ896A 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Automotive-Grade ProASIC Flash Family FPGAs
APA150-TQB 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA150-TQES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs