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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA150-PQG208A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 122/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 150K 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 158
闁€鏁�(sh霉)锛� 150000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
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ProASICPLUS Flash Family FPGAs
2- 38
v5.9
Table 2-24 DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V)
Applies to Military Temperature and MIL-STD-883B Temperature Only
Symbol
Parameter
Conditions
Military/MIL-STD-883B1
Units
Min.
Typ.
Max.
VOH
Output High Voltage
3.3 V I/O, High Drive, High Slew
(OB33PH)
3.3V I/O, High Drive, Normal/
Low Slew (OB33PN/OB33PL)
3.3 V I/O, Low Drive, High/
Normal/Low
Slew
(OB33LH/
OB33LN/OB33LL)
IOH = 鈥�8 mA
IOH = 鈥�16 mA
IOH = 鈥�3mA
IOH = 鈥�8mA
IOH = 鈥�3 mA
IOH = 鈥�8 mA
0.9
V
DDP
2.4
0.9
V
DDP
2.4
0.9
V
DDP
2.4
V
VOL
Output Low Voltage
3.3 V I/O, High Drive, High Slew
(OB33PH)
3.3V I/O, High Drive, Normal/
Low Slew (OB33PN/OB33PL))
3.3 V I/O, Low Drive, High/
Normal/Low
Slew
(OB33LH/
OB33LN/OB33LL)
IOL = 12 mA
IOL = 17 mA
IOL = 28 mA
IOL = 4 mA
IOL = 6 mA
IOL = 13 mA
IOL = 4 mA
IOL = 6 mA
IOL = 13 mA
0.1VDDP
0.4
0.7
0.1VDDP
0.4
0.7
0.1VDDP
0.4
0.7
V
VIH
2
Input High Voltage
3.3 V Schmitt Trigger Inputs
3.3 V LVTTL/LVCMOS
2.5 V Mode
1.6
2
1.7
VDDP + 0.3
V
VIL
3
Input Low Voltage
3.3 V Schmitt Trigger Inputs
3.3 V LVTTL/LVCMOS
2.5 V Mode
鈥�0.3
0.7
0.8
0.7
V
RWEAKPULLUP Weak Pull-up Resistance
(IOB33U)
VIN 鈮� 1.5 V
7
43
k
RWEAKPULLUP Weak Pull-up Resistance
(IOB25U)
VIN 鈮� 1.5 V
7
43
k
IIN
Input Current
with pull up (VIN = GND)
鈥�300
鈥�40
A
without pull up (VIN = GND or VDD)
鈥�10
10
A
IDDQ
Quiescent Supply Current
(standby)
Commercial
VIN = GND
4 or V
DD
Std.
5.015mA
IDDQ
Quiescent Supply Current
(standby)
Industrial
VIN = GND
4 or V
DD
Std.
5.0
20
mA
Notes:
1. All process conditions. Military Temperature / MIL-STD-883 Class B: Junction Temperature: 鈥�55 to +125掳C.
2. During transitions, the input signal may overshoot to VDDP +1.0 V for a limited time of no larger than 10% of the duty cycle.
3. During transitions, the input signal may undershoot to 鈥�1.0 V for a limited time of no larger than 10% of the duty cycle.
4. No pull-up resistor required.
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