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鍨嬭櫉锛� APA150-PQ208A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 143/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 150K 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 158
闁€鏁�(sh霉)锛� 150000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-57
Asynchronous SRAM Write
Note: The plot shows the normal operation status.
Figure 2-30 Asynchronous SRAM Write
Table 2-54 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 鈥�55掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B
Symbol txxx
Description
Min.
Max.
Units
Notes
AWRH
WADDR hold from WB
鈫�
1.0
ns
AWRS
WADDR setup to WB
鈫�
0.5
ns
DWRH
DI hold from WB
鈫�
1.5
ns
DWRS
DI setup to WB
鈫�
0.5
ns
PARGEN is inactive.
DWRS
DI setup to WB
鈫�
2.5
ns
PARGEN is active.
WPDA
WPE access from DI
3.0
ns
WPE is invalid, while PARGEN is
active.
WPDH
WPE hold from DI
1.0
ns
WRCYC
Cycle time
7.5
ns
WRMH
WB high phase
3.0
ns
Inactive
WRML
WB low phase
3.0
ns
Active
WRB, WBLKB
WADDR
WPE
DI
tAWRS
tWPDA
tAWRH
tDWRS
tWRML
tWRMH
tWRCYC
tWPDH
tDWRH
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