ProASICPLUS Flash Family FPGAs 1- 2 v5.9 ProASIC
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA075-TQ144
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 135/178闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA PROASIC+ 75K 144-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 27648
杓稿叆/杓稿嚭鏁�(sh霉)锛� 107
闁€鏁�(sh霉)锛� 75000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-TQFP锛�20x20锛�
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ProASICPLUS Flash Family FPGAs
1- 2
v5.9
ProASICPLUS Architecture
The
proprietary
ProASICPLUS
architecture
provides
granularity comparable to gate arrays.
The ProASICPLUS device core consists of a Sea-of-Tiles
(Figure 1-1). Each tile can be configured as a three-input
logic function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming
the
appropriate
flash
switch
Tiles and larger functions are connected with any of the
four levels of routing hierarchy. Flash switches are
distributed
throughout
the
device
to
provide
nonvolatile, reconfigurable interconnect programming.
Flash switches are programmed to connect signal lines to
the appropriate logic cell inputs and outputs. Dedicated
high-performance lines are connected as needed for fast,
low-skew global signal distribution throughout the core.
Maximum core utilization is possible for virtually any
design.
ProASICPLUS devices also contain embedded, two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming
options
include
synchronous
or
asynchronous operation, two-port RAM configurations,
user-defined depth and width, and parity generation or
checking.
Refer
to
the
for
more
information.
Figure 1-1 The ProASICPLUS Device Architecture
Figure 1-2 Flash Switch
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
256x9 Two Port SRAM
or FIFO Block
RAM Block
I/Os
Sensing
Switching
Switch In
Switch Out
Word
Floating Gate
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
APA075-PQ208 IC FPGA PROASIC+ 75K 208-PQFP
ASC36DRYI-S13 CONN EDGECARD 72POS .100 EXTEND
HSC40DRAI CONN EDGECARD 80POS R/A .100 SLD
GCB80DHBS CONN EDGECARD 160PS R/A .050 SLD
ABM43DRMT-S288 CONN EDGECARD EXTEND 86POS .156
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鍙冩暩(sh霉)鎻忚堪
APA075-TQ144I 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 75K 144-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
APA075-TQ896A 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Automotive-Grade ProASIC Flash Family FPGAs
APA075-TQB 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA075-TQES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA075-TQG100 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 75K 100-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�