ProASICPLUS Flash Family FPGAs v5.9 2-9 The TAP controller receives two control " />
參數(shù)資料
型號： APA075-TQ100I
廠商： Microsemi SoC
文件頁數(shù)： 90/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 75K 100-TQFP
標準包裝： 90
系列： ProASICPLUS
RAM 位總計： 27648
輸入/輸出數(shù)： 66
門數(shù)： 75000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
供應商設(shè)備封裝： 100-TQFP（14x14）
ProASICPLUS Flash Family FPGAs
v5.9
2-9
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles. The TRST pin
may also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
ProASICPLUS devices support three types of test data
registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other
register needs to be accessed in a device. This speeds up
test data transfer to other devices in a test data path.
The 32-bit device identification register is a shift register
with four fields (lowest significant byte (LSB), ID number,
part number and version). The boundary-scan register
observes and controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output, and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Figure 2-10 TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
Select-DR-
Scan
Capture-DR
Shift-DR
Exit-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-
Scan
Capture-IR
Shift-IR
Exit-IR
Pause-IR
Exit2-IR
Update-IR
1
0
1
0
00
1
00
1
0
1
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA075-TQ144 功能描述:IC FPGA PROASIC+ 75K 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設(shè)備封裝:256-FPBGA（17x17）
APA075-TQ144I 功能描述:IC FPGA PROASIC+ 75K 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設(shè)備封裝:256-FPBGA（17x17）
APA075-TQ896A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs
APA075-TQB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA075-TQES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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