ProASICPLUS Flash Family FPGAs 2- 70 v5.9 Synchronous FIFO Read, Pipeline Mode O" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA075-FG144A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 158/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 75K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 27648
杓稿叆/杓稿嚭鏁�(sh霉)锛� 100
闁€鏁�(sh霉)锛� 75000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASICPLUS Flash Family FPGAs
2- 70
v5.9
Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-43 Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-66 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 鈥�55掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
ECBA
New EMPTY access from RCLKS
鈫�
3.0*
ns
FCBA
FULL
鈫� access from RCLKS 鈫�
3.0*
ns
ECBH, FCBH,
THCBH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RCLKS
鈫�
1.0
ns
Empty/full/thresh are invalid from the end of
hold until the new access is complete
OCA
New DO access from RCLKS
鈫�
2.0
ns
OCH
Old DO valid from RCLKS
鈫�
0.75
ns
RDCH
RDB hold from RCLKS
鈫�
0.5
ns
RDCS
RDB setup to RCLKS
鈫�
1.0
ns
RPCA
New RPE access from RCLKS
鈫�
4.0
ns
RPCH
Old RPE valid from RCLKS
鈫�
1.0
ns
HCBA
EQTH or GETH access from RCLKS
鈫�
4.5
ns
Note: *At fast cycles, ECBA and FCBA = MAX (7.5 ns 鈥� CMS), 3.0 ns.
RCLK
RPE
RDATA
EMPTY
EQTH, GETH
FULL
Old Data Out
New Valid Data Out
RDB
Cycle Start
Old RPE Out
New RPE Out
tECBH, tFCBH
tRDCH
tRDCS
tOCA
tECBA, tFCBA
tTHCBH
tHCBA
tCMH
tCML
tCCYC
tRPCH
tOCH
tRPCA
鐩搁棞(gu膩n)PDF璩囨枡
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APA075-FG896A 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Automotive-Grade ProASIC Flash Family FPGAs
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APA075-FGES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA075-FGG144 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 75K 144-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�