參數資料
型號: AN79L07
廠商: PANASONIC CORP
元件分類: 基準電壓源/電流源
英文描述: 3-pin negative output voltage regulator (100 mA type)
中文描述: 7 V FIXED NEGATIVE REGULATOR, PBCY3
封裝: PLASTIC, SSIP-3
文件頁數: 10/12頁
文件大?。?/td> 175K
代理商: AN79L07
AN79Lxx/AN79LxxM Series
10
SFF00006CEB
I
Usage Notes
1. Cautions for a basic circuit
C
I
: When a wiring from a smoothing circuit to a three-pin regulator
is long, it is likely to oscillate at output. A capacitor of 0.1
μ
F to
0.47
μ
F should be connected near an input pin.
C
O
: Deadly needed to prevent from oscillation (0.33
μ
F to 1.0
μ
F). It
is recommended to use a capacitor of a small internal imped-
ance (ex. tantalum capacitor) when using it under a low tem-
perature.
When any sudden change of load current is likely to occur, con-
nect an electrolytic capacitor of 10
μ
F to 100
μ
F to improve a
transitional response of output voltage.
D
i
: Normally unnecessary. But add it in the case that there is a
residual voltage at the output capacitor Co even after switching
off the supply power because a current is likely to flow into an
output pin of the IC and damage the IC.
2. Other caution items
1) Short-circuit between the input pin and GND pin
If the input pin is short-circuitted to GND or is cut
off when a large capacitance capacitor has been con-
nected to the IC's load, a voltage of a capacitor con-
nected to an output pin is applied between input/out-
put of the IC and this likely results in damage of the
IC. It is necessary, therefore, to connect a diode, as
shown in figure 2, to counter the reverse bias between
input/output pins.
2) Floating of GND pin
If a GND pin is made floating in an operating mode, an unstabilized input voltage is outputted. In this case, a
thermal protection circuit inside the IC does not normally operate. In this state, if the load is short-circuited or
overloaded, it is likely to damage the IC.
I
Application Circuit Example
Figure 1
C
O
V
O
C
I
V
I
D
i
1
3
2
In
GND
Out
Figure 2
C
O
Output
1
3
2
+
V
O
2
μ
F
1
μ
F
I
Bias
AN79Lxx
3
1
2
R
2
R
1
V
O
'
V
I
Input
Common
Output
|
V
O
|
=
V
O
' 1
+
+
I
Q
R
1
R
2
R
1
+
+
Note) V
O
varies due to sample to sample variation of I
Bias
.
Never fail to adjust individually with R
1
.
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