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參數(shù)資料
| 型號： | AN6448NFBP |
| 廠商： | PANASONIC CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | CAP 120PF 50V CERAMIC MONO 5% |
| 中文描述： | TELEPHONE SPEECH CKT, PQFP64 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 156K |
| 代理商： | AN6448NFBP |
I
Logic Specifications
(Basic Block Diagrams)
Latch circuit
Output (cross-point SW and other controls)
Decoder
(6 bit, 48 channels)
A6
A5
A4
A3
A2
A1
Clock
Clock
Data
Strobe
Data
Strobe
D
(A6)
(A5)
(A4)
(A3)
(A2)
(A1)
(D)
1
0
0
1
1
0
1
Reset
Decoder
Shift register
Time charts (assuming the address h26 latch is to be set)
1. Data is read into the shift register in synchronization with a
rising edge of the clock, with the higher data being shifted
sequentially on a first-come highest-bit basis.
2. When the strobe is low, data is shifted sequentially on the
sift register in synchronization with the clock. Data on the
latch circuit will not change.
3. When the strobe goes high, the latched data whose address
is represented by the highest 6-bit of the shift register is
updated. Latched data is set when the least significant bit is
1, and reset when the bit is 0.
4. Referring to 3 above, if the address is h00 (the highest 6-
bit of the shift register are all 0s), the latch circuit is
cleared (all reset) regardless of the data content.
5. At power-on, the latch circuit is cleared (by power-ON reset).
I
Pin Descriptions (cont.)
I
O
PD2
PDI
63
64
0 to 3V depending
on V
L
Same as above
V
L
– 33
×
I
L
Z
is 1.5 to 2k
on the IC
side. It must be adjusted to
600
by inserting a 820
resistor between V
L
and GND.
DC
DC
V
L
33
15
64
63
2
P
33
820
100
μ
R40
64
V
L
Line current bypass (2) :
Line current is bypassed from
this pin through R39 to GND.
R39 must be 1/2 W or more.
Line current bypass (1) :
Line current is bypassed from
this pin through R40 to Pinw.
R40 must be 1/2 W or more.
Description
Waveform
Remarks
PinNo.
Symbol
I/O
Equivalent Circuit
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