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參數(shù)資料
| 型號： | AN3672NFBP |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Audio signal processor IC for HiFi VCR incorporating EIAJ sound multiplex system |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | QFH-64 |
| 文件頁數(shù)： | 22/29頁 |
| 文件大?。?/td> | 229K |
| 代理商： | AN3672NFBP |
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AN3672NFBP
ICs for VCR
22
I
Application Notes (continued)
3. I
2
C bus of this IC (continued)
3) Auto increment function
SLAVE ADDR
Acknowledge bit
Start condition
Stop condition
S
A
A
A
P
Sub ADDR
*
Data 0
A
Data 1
A
Data 2
Sub ADDR
10000000
(HEX: 80)
11000000
(HEX: C0)
Contents
00 to 03 data of sub ADDR can be
controlled by the above format.
00 to 05 data of sub ADDR can be
controlled by the above format.
Once the data is inputted as shown above, the specified sub-address data is set to Data 0, one increment data
to Data 1, further one increment data to Data 2. In this way, the plural data can be controlled at one time.
4) VCO f
O
auto adjusting manual
1. Power on
2. Setting 1 (INSW mute
=
On)
IC mode setting:Rec. (
*
0 D7
=
1)
Power save
=
Off (
*
3 Except for D6 and D7
=
1)
Serial
*
6 D1 0
→
1
INSW Mute
Ex.
*
6 0 0 0 0 0 0 1 0
3. Setting 2 (Selection of f
SC
frequency to be used.)
Sub-address
*
6
D5
D4 f
SC
frequency
0
0
3.58 MHz
0
1
4.43 MHz
1
0
7.16 MHz
1
1
8.86 MHz
Ex.
When you use f
SC
=
7.16 MHz,
*
6
0 0 1 0 0 0 1 0
f
SC
select
INSW mute continues
4. Adjustment start (f
O
adj. start
=
On)
Ex.
f
O
adj. start
Serial
*
6
D6
0
→
1
*
6
0 1 1 0 0 0 1 0
Setting hitherto continues
5. Adjustment completion
ENV det. output (pin 28) potential
Informs of completion with low to high
6. Setting cancellation
f
O
adj. start
=
Off
INSW mute.
=
Off
Serial
Serial
*
6
*
6
D6
D1
1
→
0
1
→
0
7. Transmission of normal data
Note) Input level of f
SC
is 100 mV[p-p] to 500 mV[p-p].
Wait
1.5 s or more
Wait
0.1 s or more
Max.
within 0.5 s
Approx. 0.5 V
Approx. 4 V
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