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參數(shù)資料
| 型號： | AN2526NFH |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Automotive LCD TV signal processor IC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 31/35頁 |
| 文件大?。?/td> | 442K |
| 代理商： | AN2526NFH |
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AN2526NFH
31
SDB00080AEB
I
Technical Data (continued)
1. Three-wire control mode (continued)
4) Mode setup channel bit-map. (continued)
ch.9: Y-aperture gain adjustment
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
00h, 01h: Test mode
ch.15: RGB contrast adjustment
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
POL mode
1
1
1
1
0
Internal POL 1H reverse mode
1
External POL 1H reverse mode
2. I
2
C control mode
A serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of
signal lines of data and shift clock.
When a slave address after setting a start condition matches the address on the IC side, you can receive the data to
be transmitted from then. Once the stop condition is set up, the next transmitting data will be ignored until the start
condition is set up.
There are two kinds of transfer mode: an auto-increment mode which does not transmit sub-address, and data
upgrade mode which transmits sub-address + data by 2 bites.
The typical models of transmitting sequence are shown below:
1) Start condition
When the S data changes from high-level to low-level at SCLK
=
high-level, a data receiving mode becomes
available.
2) Slave address transfer
The slave address of the AN2526NFH is 88h at pin 49
=
high-level and 8Ah at pin 49
=
low-level.
Sub address transfer
Acknowledge bit
1
Pin 48
S-data
Pin 47
SCLK
2
3
4
5
6
7
8
9
1
2
Start condition
3) Sub address transfer
When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded
as the data block.
Data transfer
Slave address transfer
Acknowledge bit
1
D7
D6
D5
D4
D3
D2
D1
D0
Pin 48
S-data
Pin 47
SCLK
2
3
4
5
6
7
8
9
8
9
1
2
Data transfer mode bit
"1": Data update mode
"0": Auto increment mode
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