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參數(shù)資料
| 型號： | AN1746 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Migrating from the MC68HC705K1 to the MC68HC705KJ1 |
| 中文描述： | 從MC68HC705K1遷移到MC68HC705KJ1 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 308K |
| 代理商： | AN1746 |
Application Note
AN1746
Figure 7. Port B Data Register (PORTB)
Figure 8. Port B Data Direction Register (DDRB)
Figure 9. Pulldown Register B (PDRB)
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See
Note
See
Note
PB3
PB2
See
Note
See
Note
Write:
Reset:
Unaffected by reset
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will en-
sure that the pulldown devices are enabled, thus properly terminating them.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See
Note
See
Note
DDRB3
DDRB2
See
Note
See
Note
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will en-
sure that the pulldown devices are enabled, thus properly terminating them.
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See
Note
See
Note
PDIB3
PDIB2
See
Note
See
Note
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will en-
sure that the pulldown devices are enabled, thus properly terminating them.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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