參數(shù)資料
型號(hào)： AN15865A
廠商： PANASONIC CORP
元件分類： 運(yùn)動(dòng)控制電子
英文描述： The video switch IC including the synchronous separation function for TV
中文描述： 10-CHANNEL, AUDIO/VIDEO SWITCH, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 15/37頁(yè)
文件大?。?/td> 460K
代理商： AN15865A
AN15865A
15
SDB00102AEB
I
2
C Bus Conditions
0
D1
R/W
D0
0
D4
1/0
D3
1
D2
0
0
1
84/8C
85/8D
D6
D5
D7
Sub
Address
Note) The change of D3 data is performed by control of a SLVADR terminal
Control Register
continue
AS
DATA
(X + 1)
DATA
(X + 2)
AS
DATA
(X)
AS
AS
Sub Address
(X)
Slave Address
(84 or 8C)
S
Note) AS = ACK from Slave
100 : 576i / 50
101 : 576p / 50
110 : 1 080i / 50
111 : 720p / 50
000 : 480i / 60
001 : 480p / 60
010 : 1 080i / 60
011 : 720p / 60
00 : through
01 : CCIR standard
10 : BTA standard
11 : GBR matrix
00 : through
01 : CCIR standard
10 : BTA standard
11 : GBR matrix
01 : sync on CV/Y
10 11 : free-run
OUT4 signal select
OUT3 signal select
01
OUT5 signal select
OUT5 sync
0 : AFC
1 : independent
free-run priority
0 : fixing
1 : auto
distinction use
OUT5
sync
distinction
02
HVout2 polarity
0 : positive
1 : negative
Dummy sync mode
Control
(When 02/D7, D6 =
'11')
OUT5 matrix
OUT4 matrix
03
OUT5 GAIN
0 : 0 dB
1 : 6 dB
OUT4 GAIN
0 : 0 dB
1 : 6 dB
SY3/SC3 GAIN
0 : 0 dB
1 : 6 dB
CV3 GAIN
0 : 0 dB
1 : 6 dB
SY2/SC2 GAIN
0 : 0 dB
1 : 6 dB
CV2 GAIN
0 : 0 dB
1 : 6 dB
SY1/SC1 GAIN
0 : 0 dB
1 : 6 dB
CV1 GAIN
0 : 0 dB
1 : 6 dB
04
Field monitor sel
0 : F1 / F2 out
1 : clock moni out
00 : 0 V
01 : 1.9 V
10 : indefinite
11 : 4.5 V
OUT1 DCOUT
OUT5 LPF
0 : through
1 : LPF ON
OUT4 LPF
0 : through
1 : LPF ON
OUT3 LPF
0 : through
1 : LPF ON
OUT2 LPF
0 : through
1 : LPF ON
OUT1 LPF
0 : through
1 : LPF ON
05
Australia free-run
0 : except Australia
1 : Australia mode
input10 BR/UV sel
0 : BR select
1 : UV select
input9 BR/UV sel
0 : BR select
1 : UV select
input8 BR/UV sel
0 : BR select
1 : UV select
input7 U/SY sel
0 : SY select
1 : U select
input6 U/SY sel
0 : SY select
1 : U select
input5 U/SY sel
0 : SY select
1 : U select
input4 U/SY sel
0 : SY select
1 : U select
06
test70
test71
test72
test73
test74
test75
test76
test77
07
test80
test81
test82
test83
test84
test85
test86
test87
08
OUT2 signal select
OUT1signal select
00
D1
D0
D4
D3
D2
D6
D5
D7
Sub
Address
Note) Please send data "00" to sub-address "07" and "08".
R/W = 0
y
The AN15865A in I
2
C bus control performs switch mode selection, matrix selection, gain selection, LPF selection, synchronous
mode selection and freerun mode selection through a control register and detects the system status, aspect and pin information
through a status register.
The upper seven address bits are allocated to the slave address while the LSB is allocated to the R/W bit.
The R/W bit corresponds to the control register with with the bit set to 0 and corresponds to the status register with the bit set to 1.
y
The AN15865A selects slave address 84 or 8C(hex) according to the status of the SLVADR pin.
Address 84(hex) will be selected with the SLVADR pin grounded the the GND side. Address 8C(hex) will be selected with the pin
grounded to the 5-V line.
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