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參數(shù)資料
| 型號： | AN12942B |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Audio signal processing IC for notebook PC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO56 |
| 封裝： | 0.300 INCH, PLASTIC, HSOP-56 |
| 文件頁數(shù)： | 25/31頁 |
| 文件大?。?/td> | 577K |
| 代理商： | AN12942B |
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25
SDC00047AEB
AN12942B
Application Notes (continued)
3
.
Speaker amplifier circuit block
Following block diagrams is speaker amplifier circuit.
1) The gain of the speaker amplifier system is
+
17.0 dB.
2) The entry impedance of pin 45, pin 44 becomes 18 k
.
3) It is possible to adjust to the direction which lowers a gain in adding resistance to pin 28, pin 27.
Gain at insert a resistance
4) By the power save control by pin 50, the speaker can be output in the save mute.
5) For the pop sound measure at the time of power on, delay from the standby cancellation by pin 32 and cancel a speaker save
mute.
Note
Design reference value
Parameter
Equal to or more than 8
of loads
Ability of the output drive
Note) *: The time of the warp (to 5th of THD)
of 10% of output.
1 W : at 8
of loads
Maximum output level
Note) *: But, it limits into the sound band range
of equal to or less than 50 kHz
.
Equal to or less than 1
Output impedance
Note) *: It done the change being of
±
10%
because there is a change of the inner
resistance.
18 k
Input impedance
+
17.0 dB
The input/output gain
Design reference value
45
Mute
SP input L-ch.
AGC
+
10
18k
SP input R-ch.
3 dB
Offset
cancel
Det.
47
44
Mute
AGC
18k
3 dB
Offset
cancel
46
+
14 dB
50
Save
54
SP output L-ch.
+
SP output L-ch.
+
55
52
53 SP output L-ch.
SP output L-ch.
3
2 SP output R-ch.
+
SP output R-ch.
+
5
4 SP output R-ch.
SP output R-ch.
SP save
+
14 dB
+
14 dB
+
14 dB
Pin 44
Pin 45
R
18k
Gain
=
20 log 18 k
+
17 dB
R
+
18 k
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