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參數(shù)資料
| 型號： | AN-24 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | A Simplified Test Set for Op Amp Characterization |
| 中文描述： | 一種簡化的測試設(shè)置運(yùn)算放大器表征 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 412K |
| 代理商： | AN-24 |
basic function from which the pulse and triangular wave are
derived, the pulse is referenced to the leading edge of the
square wave, and the triangular wave is the inverted and
integrated square wave.
Amplifier A
4
is an astable multivibrator generating a square
wave from positive to negative saturation. The amplitude of
this square wave is approximately
g
19V. The square wave
frequency is determined by the ratio of R
18
to R
16
and by
the time constant, R
17
C
9
. The operating frequency is stabi-
lized against temperature and power regulation effects by
regulating the feedback signal with the divider R
19
, D
5
and
D
6
.
Amplifier A
5
is a monostable multivibrator triggered by the
positive going output of A
4
. The pulse width of A
5
is deter-
mined by the ratio of R
20
to R
22
and by the time constant
R
21
C
10
. The output pulse of A
5
is an approximately 1% duty
cycle pulse from approximately
b
19V to
a
19V.
Amplifier A
6
is a dc stabilized integrator driven from the am-
plitude-regulated output of A
4
. Its output is a
g
5V triangular
wave. The amplitude of the output of A
6
is determined by
the square wave voltage developed across D
5
and D
6
and
the time constant R
adj
C
14
. DC stabilization is accomplished
by the feedback network R
24
, R
25
, and C
15
. The ac attenua-
tion of this feedback network is high enough so that the
integrator action at the square wave frequency is not de-
graded.
Operating frequency of the function generator may be var-
ied by adjusting the time constants associated with A
4
, A
5
,
and A
6
in the same ratio.
TEST CIRCUIT
A complete schematic diagram of the test circuit is shown in
Figure 7. The test circuit accepts the outputs of the power
supplies and function generator and provides horizontal and
vertical outputs for an X-Y oscilloscope, which is used as
the measurement system.
The primary elements of the test circuit are the feedback
buffer and integrator, comprising amplifier A
7
and its feed-
back network C
16
, R
31
, R
32
, and C
17
, and the differential
amplifier network, comprising the device under test and the
feedback network R
40
, R
43
, R
44
, and R
52
. The remainder of
the test circuit provides the proper conditioning for the de-
vice under test and scaling for the oscilloscope, on which
the test results are displayed.
The amplifier A
8
provides a variable amplitude source of
common mode signal to exercise the amplifier under test
over its common mode range. This amplifier is connected as
a non-inverting gain-of-3.6 amplifier and receives its input
from the triangular wave generator. Potentiometer R
37
al-
lows the output of this amplifier to be varied from
g
0 volts
to
g
18 volts. The output of this amplifier drives the differen-
tial input resistors, R
43
and R
44
, for the device under test.
The resistors R
46
and R
47
are current sensing resistors
which sense the input current of the device under test.
These resistors are switched into the circuit in the proper
sequence by the field effect transistors Q
6
and Q
7
. Q
6
and
Q
7
are driven from the square wave output of the function
generator by the PNP pair, Q
10
and Q
11
, and the NPN pair,
Q
8
and Q
9
. Switch sections S
1b
and S
1c
select the switch-
ing sequence for Q
8
and Q
9
and hence for Q
6
and Q
7
. In
the bias current test, the FET drivers, Q
8
and Q
9
, are
switched by out of phase signals from Q
10
and Q
11
. This
opens the FET switches Q
6
and Q
7
on alternate half cycles
of the square wave output of the function generator. During
the offset voltage, offset current test, the FET drivers are
operated synchronously from the output of Q
11
. During the
transfer function test, Q
6
and Q
7
are switched on continu-
ously by turning off Q
11
. R
42
and R
45
maintain the gates of
the FET switches at zero gate to source voltage for maxi-
mum conductance during their on cycle. Since the sources
of these switches are at the common mode input voltage of
the device under test, these resistors are connected to the
output of the common mode driver amplifier, A
8
.
The input for the integrator-feedback buffer, A
7
, is selected
by the FET switches Q
4
and Q
5
. During the bias current and
offset voltage offset current tests, A
7
is connected as an
integrator and receives its input from the output of the de-
vice under test. The output of A
7
drives the feedback resis-
tor, R
40
. In this connection, the integrator holds the output
of the device under test near ground and serves to amplify
the voltages corresponding to bias current, offset current,
and offset voltage by a factor of 1,000 before presenting
them to the measurement system. FET switches Q
4
and Q
5
are turned on by switch section S
1b
during these tests.
FET switches Q
4
and Q
5
are turned off during the transfer
function test. This disconnects A
7
from the output of the
device under test and changes it from an integrator to a
non-inverting unity gain amplifier driven from the triangular
wave output of the function generator through the attenua-
tor R
33
and R
34
and switch section S
1a
. In this connection,
amplifier A
7
serves two functions; first, to provide an offset
voltage correction to the input of the device under test and,
second, to drive the input of the device under test with a
g
2.5 mV triangular wave centered about the offset voltage.
During this test, the common mode driver amplifier is dis-
abled by switch section S
1a
and the vertical input of the
measurement oscilloscope is transferred from the output of
the integrator-buffer, A
7
, to the output of the device under
test by switch section S
1d
. S
2a
allows supply voltages for
the device under test to be set at
g
5,
g
10,
g
15, or
g
20V.
S
2b
changes the vertical scale factor for the measurement
oscilloscope to maintain optimum vertical deflection for the
particular power supply voltage used. S
4
is a momentary
contact pushbutton switch which is used to change the load
on the device under test from 10 k
X
to 2 k
X
.
A delay must be provided when switching from the input
tests to the transfer function tests. The purpose of this delay
is to disable the integrator function of A
7
before driving it
with the triangular wave. If this is not done, the offset cor-
rection voltage, stored on C
16
, will be lost. This delay be-
tween opening FET switch Q
4
, and switch Q
5
, is provided by
the RC filter, R
35
and C
19
.
Resistor R
41
and diodes D
7
and D
8
are provided to control
the integrator when no test device is present, or when a
faulty test device is inserted. R
41
provides a dc feedback
path in the absence of a test device and resets the integra-
tor to zero. Diodes D
7
and D
8
clamp the input to the integra-
tortoapproximately
g
.7voltswhenafaultydeviceisinserted.
FET switch Q
1
and resistor R
28
provide a ground reference
at the beginning of the 50-ohm-source, offset-voltage trace.
This trace provides a ground reference which is indepen-
dent of instrument or oscilloscope calibration. The gate of
Q
1
is driven by the output of monostable multivibrator A
5
,
and shorts the vertical oscilloscope drive signal to ground
during the time that A
5
output is positive.
Switch S
3
, R
27
, and R
28
provide a 5X scale increase during
input parameter tests to allow measurement of amplifiers
with large offset voltage, offset current, or bias current.
Switch S
5
allows amplifier compensation to be changed for
101 or 709 type amplifiers.
5
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