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參數(shù)資料
| 型號： | AMPAL22V10 |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | PAL |
| 英文描述： | PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device |
| 中文描述： | PAL22V10家庭，AmPAL22V10 / 24針的TTL多功能PAL制式設(shè)備 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 184K |
| 代理商： | AMPAL22V10 |
AMD
2-201
PAL22V10 Family
Registered Output Configuration
Each macrocell of the PAL22V10 includes a D-type flip-
flop for data storage and synchronization. The flip-flop
is loaded on the LOW-to-HIGH transition of the clock in-
put. In the registered configuration (S
1
= 0), the array
feedback is from
Q
of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(S
1
= 1). In the combinatorial configuration the feedback
is from the pin.
D
Q
Q
CLK
SP
AR
Registered/Active Low
S
0
= 0
S
1
= 0
Combinatorial/Active Low
S
0
= 0
S
1
= 1
D
Q
Q
CLK
SP
AR
Registered/Active High
S
0
= 1
S
1
= 0
Combinatorial/Active High
S
0
= 1
S
1
= 1
16559C-5
Figure 2. Macrocell Configuration Options
Programmable Three-State Outputs
Each output has a three-state output buffer with three-
state control. A product term controls the buffer, allow-
ing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional I/O pin, and may be con-
figured as a dedicated input if the buffer is always dis-
abled.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is controlled by programmable bit S
0
in the
output macrocell, and affects both registered and com-
binatorial outputs. Selection is automatic, based on the
design specification and pin definitions.
Preset/Reset
For initialization, the PAL22V10 has Preset and Reset
product terms. These terms are connected to all regis-
tered outputs. When the Synchronous Preset (SP)
product term is asserted high, the output registers will be
loaded with a HIGH on the next LOW-to-HIGH clock
transition. When the Asynchronous Reset (AR) product
term is asserted high, the output registers will be imme-
diately loaded with a LOW independent of the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PAL22V10 will de-
pend on the programmed output polarity. The V
CC
rise
must be monotonic and the reset delay time is 1000 ns
maximum.
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