參數(shù)資料
型號(hào)： AMIS49587C5871G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 15/55頁(yè)
文件大小： 0K
描述： IC MODEM PLC 50/60MHZ 28PLCC
標(biāo)準(zhǔn)包裝： 37
波特率： 可選
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 管件
AMIS49587
http://onsemi.com
22
6.2
TRANSMITTER PATH DESCRIPTION (SFSK
MODULATOR)
For the generation of the space and mark frequencies, the
direct digital synthesis (DDS) of the sine wave signals is
performed under the control of the microprocessor. After a
signal conditioning step, a digital to analog conversion is
performed. As for the receive path, a sigma delta modulation
technique is used. In the analog domain, the signal is low
pass filtered, in order to remove the high frequency
quantization noise, and passed to the automatic level
controller (ACL) block, where the level of the transmitted
signal can be adjusted. The determination of the signal level
is done through the sense circuitry.
Figure 17. Transmitter Block Diagram
Transmitter (SFSK Modulator)
ARM
Interface
&
Control
TX_OUT
Transmit Data
& Sine Synthesizer
D/A
LP
Filter
ALC
control
ALC_IN
TO RECEIVER
fMI
fMQ
fSI
fSQ
TX_EN
6.2.1 ARM Interface and Control
The interface with the ARM consists in a 8bit data
registers R_TX_DATA, 2 control registers R_TX_CTRL
and R_ALC_CTRL, a flag TX_RXB defining transmit and
receive and 2 16bit wide frequency step registers R_FM
and R_FS defining fM (mark frequency = data 1) and fS
(space frequency = data 0). All these registers are memory
mapped. Some of them are for internal use only and cannot
be accessed by the user.
The processing of the physical frame (preamble, MAC
address, CRC) is done by the ARM.
6.2.2 Sine Wave Generator
A sine wave is generated with a direct digital synthesizer
DDS. The synthesizer generates in transmission mode a sine
wave either for the space frequency (fS, data 0) or for the
mark frequency (fM, data1). In reception the synthesizer
generates the sine and cosine waves for the mixing process,
fSI, fSQ, fMI, fMQ (space and mark signals in phase and
quadrature). The space and mark frequencies are defined in
an individual step 16 bit wide register.
Table 24. FS AND FM STEP REGISTERS
ARM
Register
Hard
Reset
Soft
Reset
Description
R_FS[15:0]
0000h
Step register for the
space frequency fS
R_FM[15:0]
0000h
Step register for the
mark frequency fM
The space and mark frequency can be calculated as:
fS = R_FS[15:0]_dec x fDDS/218
fM = R_FM[15:0]_dec x fDDS/218
Or the content of both R_FS[15:0] and R_FM[15:0] are
defined as:
R_FS[15:0]_dec = Round(218 x fS/fDDS)
R_FM[15:0]_dec = Round(218 x fM/fDDS)
Where fDDS = 3 MHz is the direct digital synthesizer
clock frequency.
After a hard or soft reset or at the start of the transmission
(when TX_RXB goes from 0 to 1) the phase accumulator
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