(VCC = 4.75 to 5.2" />
參數(shù)資料
型號(hào)： AMIS42770ICAW1RG
廠商： ON Semiconductor
文件頁(yè)數(shù)： 13/13頁(yè)
文件大小： 0K
描述： TRANSCEIVER CAN DUAL HS 20-SOIC
標(biāo)準(zhǔn)包裝： 1
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： CAN
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 1115 (CN2011-ZH PDF)
其它名稱： 766-1010-6
AMIS42770
http://onsemi.com
9
Table 6. DC AND TIMING CHARACTERISTICS
(VCC = 4.75 to 5.25 V; Tjunc = 40 to +150°C; RLT = 60 W unless specified otherwise.)
Symbol
Unit
Max.
Typ.
Min.
Conditions
Parameter
BUS LINES (pins CANH1/2 and CANL1/2)
Vi(dif)(th)
Differential receiver threshold
voltage
5 V < VCANLx < +12 V;
5 V < VCANHx < +12 V;
see Figure 7
0.5
0.7
0.9
V
Vihcm(dif) (th)
Differential receiver threshold
voltage for high common
mode
35 V < VCANLx < +35 V;
35 V < VCANHx < +35 V;
see Figure 7
0.3
0.7
1.05
V
Vi(dif) (hys)
Differential receiver input
voltage hysteresis
35 V < VCANL < +35 V;
35 V < VCANH < +35 V;
see Figure 7
50
70
100
mV
Ri(cm)(CANHx)
Commonmode input resist-
ance at pin CANH1/2
15
26
37
KW
Ri(cm) (CANLx)
Commonmode input resist-
ance at pin CANL1/2
15
26
37
KW
Ri(cm)(m)
Matching between pin CANH1/2
and pin CANL1/2 common
mode input resistance
VCANHx = VCANLx
3
0
+3
%
Ri(dif)
Differential input resistance
25
50
75
KW
Ci(CANHx)
Input capacitance at pin
CANH1/2
VTx0 = VCC; not tested
7.5
20
pF
Ci(CANLx)
Input capacitance at pin
CANL1/2
VTx0 = VCC; not tested
7.5
20
pF
Ci(dif)
Differential input capacitance
VTx0 = VCC; not tested
3.75
10
pF
ILI(CANHx)
Input leakage current at pin
CANH1/2
VCC < PORL_VCC;
5.25 V < VCANHx < 5.25 V
350
170
350
mA
ILI(CANLx)
Input leakage current at pin
CANL1/2
VCC < PORL_VCC;
5.25 V < VCANLx < 5.25 V
350
170
350
mA
VCMpeak
Commonmode peak during
transition from dom → rec or
rec → dom
See Figure 11
1000
mV
VCMstep
Difference in commonmode
between dominant and recess-
ive state
See Figure 11
250
mV
THERMAL SHUTDOWN
Tj(sd)
Shutdown junction temperature
150
°C
TIMING CHARACTERISTICS (see Figures 8 and 9)
td(TxBUSon)
Delay Tx0/Text to bus active
40
85
120
ns
td(TxBUSoff)
Delay Tx0/Text to bus inactive
30
60
115
ns
td(BUSonRX)
Delay bus active to Rx0/Rint
25
55
115
ns
td(BUSoffRX)
Delay bus inactive to Rx0/Rint
65
100
145
ns
td(ENxB)
Delay from EN1B to bus act-
ive/inactive
100
200
ns
td(TxRx)
Delay from Tx0 to Rx0/Rint
and from Text to Rx0
(direct logical path)
15 pF on the digital output
4
10
35
ns
tdom
Time out counter interval
15
25
45
ms
td(FBS)
Delay for feedback suppres-
sion release
5+
td(BUSonRX)
300
ns
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