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參數(shù)資料
| 型號： | AMIS30585C5852G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 0K |
| 描述： | IC MODEM S-FSK HALFDUPLEX 28PLCC |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 波特率： | 14.4k |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
AMIS30585
http://onsemi.com
4
Table 1. AMIS30585 PIN FUNCTIONS
No.
Name
I/O
Type
Description
1
VSSA
P
Analog ground
2
RX_OUT
Out
A
Output of input stage opamp
3
RX_IN
In
A
Positive input of input stage opamp
4
REF_OUT
Out
A
Reference output for stabilization
5
M50HZ_IN
In
A
50.60 Hz input
6
10O
In/Out
D, 5 V Safe
Programmable IO pin (open drain)
7
TDO
Out
D, 5 V Safe
Test data output
8
TDI
In
D, 5 V Safe
Test data output (internal pull down)
9
TCK
In
D, 5 V Safe
Test clock (internal pull down)
10
TMS
In
D, 5 V Safe
Test mode select (internal pull down)
11
TRSTB
In
D, 5 V Safe
Test reset bar (internal pull down, active low)
12
TX_DATA
Out
D, 5 V Safe
Data output corresponding to transmitted frequency
13
XIN
In
A
Xtal input (can be driven by an internal clock)
14
XOUT
Out
A
Xtal output (output floating when XIN driven by external clock)
15
VSS
P
Digital ground
16
VDD
P
3.3 V digital supply
17
TXD
Out
D, 5 V Safe
SCI transmit output (open drain)
18
RXD
In
D, 5 V Safe
SCI receive input (Schmitt trigger output)
19
IO2
In/Out
D, 5 V Safe
Programmable IO pin + interrupt (open drain)
20
BR1
In
D, 5 V Safe
SCI baud rate selection
21
BR0
In
D, 5 V Safe
SCI baud rate selection
22
IO1
In/Out
D, 5 V Safe
Programmable IO pin (open drain)
23
RESB
In
D, 5 V Safe
Master reset bar (Schmitt trigger input, active low)
24
TEST
In
D
Test enable (internal pull down)
25
TX_ENB
Out
D, 5 V Safe
TX enable bar (open drain)
26
TX_OUT
Out
A
Transmitter output
27
ALC_IN
In
A
Automatic level control input
28
VDDA
P
3.3 V analog supply
P:
A:
D:
5 V Safe:
Power pin
Analog pin
Digital pin
IO that support the presence of 5 V on bus line
Out:
In:
In/Out:
Output signal
Input signal
Bidirectional pin
Pin 1: VSSA
VSSA is the analog ground supply pin. It is strongly
recommended putting a decoupling capacitance between
this pin and the VDDA pin. This capacitance value is:
100 nF
±10 percent ceramic. Connection path of the
capacitance to the VSSA and VDDA on the PCB should be
kept as short as possible in order to minimize the serial
resistance.
Pin 2: RX_OUT
RX_OUT is the output analog pin of the receiver low
noise input opamp. This opamp is in a negative feedback
configuration. To know how to use this pin, refer to the
explanations given for pin RX_IN.
Pin 3: RX_IN
RX_IN is the positive analog input pin of the receiver low
noise input opamp. Together with the pins two and three,
an active high pass filter is realized. This filter removes the
main frequency (50 or 60 Hz) from the received signal. The
filter characteristics are determined by external capacitors
and resistors. Typical values are given in Table 2. For these
values and after this filter, a typical attenuation of 80 dB at
50 or 60 Hz is obtained. Table 2 represents external
components connection. The present construction supposes
the presence of a previous formed with the coupling
transformer and a parallel capacitance is placed on the
mains. This last one performs a typical attenuation of 60 dB.
The combined effect of the two filters decreases the voltage
level of the main frequency well below the sensitivity of the
AMIS30585.
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