參數(shù)資料
型號(hào): AM79C989JCT
廠商: ADVANCED MICRO DEVICES INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Quad Ethernet Switching Transceiver (QuEST⑩)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 27/37頁(yè)
文件大?。?/td> 198K
代理商: AM79C989JCT
Am79C989
27
P R E L I M I N A R Y
Status Register (Reg 19)
The Status Register (Reg 19) contains Read/Only (R/
O) and Cleared on Read (COR) bits which indicate
status beyond the Auto-Negotiation status registers.
This register is duplicated for each port.
Error Mask Register (Reg 20)
The Error Mask Register (Reg 20) determines which
errors will be reported in the Summary Register (Reg
16). The Error Mask Register contains Read/Write
(R/W) or Read/Only (R/O) bits. If an error does occur
and the Mask enable bit is set the Error bit in the Sum-
mary Register (Reg 17) will not be asserted. This reg-
ister is duplicated for each port.
Table 19.
Error Mask Register (Reg 20)
Bit(s)
Name
Description
Read/
Write
Default/
Reset
15:3
Reserved
Written and read as zero.
R/O
0
2
Rate Mismatch
Error
1 = Frames received underflowed or overflowed the elasticity FIFO;
0 = No rate mismatch has occurred.
Register bit is cleared on Read.
R/O, COR
0
1
Receive Polarity
Reversed
1 = Receive polarity of the 10BASE-T receivers is reversed;
0 = Receive polarity is correct.
R/O
0
0
Jabber Error
1 = 10BASE-T transmit circuit is in the Jabber state;
0 = 10BASE-T transmit circuit not in the Jabber state.
This bit is automatically cleared when the jabber condition
terminates.
R/O
0
Bit(s)
Name
Description
Read/
Write
Default/
Reset
15:3
Reserved
Written and read as zero.
R/O
0
2
Rate Mismatch
Error Enabled
1 = Rate Mismatch Error reportable in the Summary Register;
0 = Rate Mismatch Error not reportable in the Summary Register.
R/W
0
1
Receive Polarity
Reversed Error
Enable
1 = Receive Polarity Reversed reportable in the Summary Register
as an Error;
0 = Receive Polarity Reversed bit not reportable as an error in the
Summary Register.
R/W
0
0
Jabber Error
Enable
1 = Jabber error reportable in the Summary Register;
0 = Jabber error not reportable in the Summary Register.
R/W
0
相關(guān)PDF資料
PDF描述
AM79C98 Twisted-Pair Ethernet Transceiver (TPEX)
AM79C98JC Twisted-Pair Ethernet Transceiver (TPEX)
AM79C98PC Twisted-Pair Ethernet Transceiver (TPEX)
AM79D2251 Dual Intelligent Subscriber Line Audio-Processing Circuit (ISLAC)
AM79D2251JC Dual Intelligent Subscriber Line Audio-Processing Circuit (ISLAC)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C98JC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX)
AM79C98JC/B 制造商:Advanced Micro Devices 功能描述: 制造商:Advanced Micro Devices 功能描述:Part Number Only
AM79C98JCDV/B 制造商:Advanced Micro Devices 功能描述:
AM79C98PC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX)
AM79C98PC/B 制造商:Advanced Micro Devices 功能描述:79C98PC/B