參數(shù)資料
型號(hào)： AM79C975VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 37/304頁(yè)
文件大?。?/td> 2092K
代理商： AM79C975VCW
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)
Am79C973/Am79C975
37
P R E L I M I N A R Y
pins carry the transmit output data and are connected
to the transmit side of the magnetics module.
RX+, RX-
Serial Receive Data
MLT-3/PECL
These pins are the 10BASE-T/100BASE-X port differ-
ential receiver pairs. They receive MLT-3 data and are
connected to the receive side of the magnetics module
in 100BASE-TX operation. They receive PECL NRZI
data from an external fiber optic transceiver in
100BASE-FX application. For 10BASE-T, these pins
accept the receive input data from the magnetics mod-
ule.
Input
SDI+, SDI-
Signal Detect
These pins control the selection between PECL and
MLT-3 data for the TX± and RX± pins. For 100BASE-
TX or 10BASE-T, both of these pins may be tied to
ground or left floating. This enables transmission and
reception of MLT-3 or 10BASE-T signals at the TX± and
RX± pins. For 100BASE-FX, these pins are biased at
PECL levels. They are connected to the SDI pin from
the optical transceiver module to indicate whether the
received signal is above the required threshold. If sig-
nal detect is not available, these pins should be tied to
a PECL logical 1 (SDI+ = PECL 1, SDI- = PECL 0). See
Table 2.
Input
Table 2. SDI± Settings for Transceiver Operation
IREF
Internal Current Reference
This pin serves as a current reference for the integrated
10/100 PHY. It must be connected to ground via a
12 k
resistor (1%).
Clock Interface
Input
XTAL1
Crystal Input
The internal clock generator uses a 25-MHz (50 ppm-
100 ppm) crystal that is attached to the XTAL1 and
XTAL2 pins. XTAL1 may alternatively be driven using
an external 25 MHz (50 ppm - 100 ppm) CMOS-level
clock signal when XTAL2 is left floating. The XTAL1 pin
is not 5 V tolerant and must only be driven by a 3.3 V
clock source.
Input
XTAL2
Crystal Output
The internal clock generator uses a 25 MHz (50 ppm -
100 ppm) crystal that is attached to the pins XTAL1 and
XTAL2. XTAL1 may alternatively be driven using an ex-
ternal 25 MHz (50 ppm - 100 ppm) CMOS-level clock
signal when XTAL2 is left floating.
XCLK/XTAL
External Clock/Crystal Select
When HIGH, an External Clock Source is selected by-
passing the Crystal circuit. When LOW, a Crystal is
used instead. The following table illustrates how this pin
works.
Output
Input
Serial Management Interface (SMI)
(Am79C975 only)
MCLOCK
SMI Clock
MCLOCK is the clock pin of the serial management in-
terface. MCLOCK is typically driven by an external I
2
C/
SMBus master. The Am79C975 controller will drive the
clock line low in order to insert wait states before it
starts sending out data in response to a read. The fre-
quency of the clock signal can vary between 10 kHz
and 100 kHz, and it can change from cycle to cycle.
Input/Output
Note:
MCLOCK is also capable of running at a fre-
quency as high as 2.5 MHz to allow for shorter produc-
tion test time.
MDATA
SMI Data
MDATA is the data pin of the serial management inter-
face. MDATA can be driven by an external I
2
C/SMBus
master or by the Am79C975 controller. The interface
protocol defines exactly at what time the Am79C975
controller has to listen to the MDATA pin and at what
time the controller must drive the pin.
MIRQ
SMI Interrupt
MIRQ is an asynchronous attention signal that the
Am79C975 controller provides to indicate that a man-
agement frame has been transmitted or received. The
assertion of the MIRQ signal can be controlled by a glo-
bal mask bit (MIRQEN) or individual mask bits
Input/Output
Output
SDI+
SDI-
Port Mode
TTL LOW
(<0.8 V)
TTL LOW
(<0.8 V)
MLT-3/10BASE-T
Mode
TTL HIGH
(>2.0 V)
TTL HIGH
(>2.0 V)
PECL Mode
Input Pin
Output
Pin
XCLK/XTAL
Clock Source
XATL1
XTAL2
0
Crystal
XTAL1
Don
’
t Care
1
Oscillator/
External CLK
Source
相關(guān)PDF資料
PDF描述
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KIW PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KCW PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C978AKCW Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C978AVCW Single-Chip 1/10 Mbps PCI Home Networking Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C976 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KC 制造商:Rochester Electronics LLC 功能描述:METRIC PLASTIC QUAD-RING - Bulk
AM79C976KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KD 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC)
AM79C976KF 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*