- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366551 > AM79C975KCW (ADVANCED MICRO DEVICES INC) PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C975KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 69/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C975KCW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)當(dāng)前第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)
Am79C973/Am79C975
69
P R E L I M I N A R Y
If a poll operation has revealed that the current and the
next RDTE belong to the Am79C973/Am79C975 con-
troller, then additional poll accesses are not necessary.
Future poll operations will not include RDTE accesses
as long as the Am79C973/Am79C975 controller re-
tains ownership of the current and the next RDTE.
When receive activity is present on the channel, the
Am79C973/Am79C975 controller waits for the com-
plete address of the message to arrive. It then decides
whether to accept or reject the frame based on all ac-
tive addressing schemes. If the frame is accepted, the
Am79C973/Am79C975 controller checks the current
receive buffer status register CRST (CSR41) to deter-
mine the ownership of the current buffer.
If ownership is lacking, the Am79C973/Am79C975
controller will immediately perform a final poll of the
current RDTE. If ownership is still denied, the
Am79C973/Am79C975 controller has no buffer in
which to store the incoming message. The MISS bit will
be set in CSR0 and the Missed Frame Counter
(CSR112) will be incremented. Another poll of the cur-
rent RDTE will not occur until the frame has finished.
If the Am79C973/Am79C975 controller sees that the
last poll (either a normal poll, or the final effort de-
scribed in the above paragraph) of the current RDTE
shows valid ownership, it proceeds to a poll of the next
RDTE. Following this poll, and regardless of the out-
come of this poll, transfers of receive data from the
FIFO may begin.
Regardless of ownership of the second receive de-
scriptor, the Am79C973/Am79C975 controller will con-
tinue to perform receive data DMA transfers to the first
buffer. If the frame length exceeds the length of the first
buffer, and the Am79C973/Am79C975 controller does
not own the second buffer, ownership of the current de-
scriptor will be passed back to the system by writing a
0 to the OWN bit of RMD1. Status will be written indi-
cating buffer (BUFF = 1) and possibly overflow (OFLO
= 1) errors.
If the frame length exceeds the length of the first (cur-
rent) buffer, and the Am79C973/Am79C975 controller
does own the second (next) buffer, ownership will be
passed back to the system by writing a 0 to the OWN
bit of RMD1 when the first buffer is full. The OWN bit is
the only bit modified in the descriptor. Receive data
transfers to the second buffer may occur before the
Am79C973/Am79C975 controller proceeds to look
ahead to the ownership of the third buffer. Such action
will depend upon the state of the FIFO when the OWN
bit has been updated in the first descriptor. In any case,
lookahead will be performed to the third buffer and the
information gathered will be stored in the chip, regard-
less of the state of the ownership bit.
This activity continues until the Am79C973/Am79C975
controller recognizes the completion of the frame (the
last byte of this receive message has been removed
from the FIFO). The Am79C973/Am79C975 controller
will subsequently update the current RDTE status with
the end of frame (ENP) indication set, write the mes-
sage byte count (MCNT) for the entire frame into
RMD2, and overwrite the
“
current
”
entries in the CSRs
with the
“
next
”
entries.
Receive Frame Queuing
The Am79C973/Am79C975 controller supports the
lack of RDTEs when SRAM (SRAM SIZE in BCR 25,
bits 7-0) is enabled through the Receive Frame Queu-
ing mechanism. When the SRAM SIZE = 0, then the
Am79C973/Am79C975 controller reverts back to the
PCnet PCI II mode of operation. This operation is auto-
matic and does not require any programming by the
host. When SRAM is enabled, the Receive Frame
Queuing mechanism allows a slow protocol to manage
more frames without the high frame loss rate normally
attributed to FIFO based network controllers.
The Am79C973/Am79C975 controller will store the in-
coming frames in the extended FIFOs until polling
takes place; if enabled, it discovers it owns an RDTE.
The stored frames are not altered in any way until writ-
ten out into system buffers. When the receive FIFO
overflows, further incoming receive frames will be
missed during that time. As soon as the network re-
ceive FIFO is empty, incoming frames are processed
as normal. Status on a per frame basis is not kept dur-
ing the overflow process. Statistic counters are main-
tained and accurate during that time.
During the time that the Receive Frame Queuing mech-
anism is in operation, the Am79C973/Am79C975 con-
troller relies on the Receive Poll Time Counter (CSR
48) to control the worst case access to the RDTE. The
Receive Poll Time Counter is programmed through the
Receive Polling Interval (CSR49) register. The Re-
ceived Polling Interval defaults to approximately 2 ms.
The Am79C973/Am79C975 controller will also try to
access the RDTE during normal descriptor accesses
whether they are transmit or receive accesses. The
host can force the Am79C973/Am79C975 controller to
immediately access the RDTE by setting the RDMD
(CSR 7, bit 13) to 1. Its operation is similar to the trans-
mit one. The polling process can be disabled by setting
the RXDPOLL (CSR7, bit 12) bit. This will stop the au-
tomatic polling process and the host must set the
RDMD bit to initiate the receive process into host mem-
ory. Receive frames are still stored even when the re-
ceive polling process is disabled.
Software Interrupt Timer
The Am79C973/Am79C975 controller is equipped with
a software programmable free-running interrupt timer.
The timer is constantly running and will generate an in-
terrupt STINT (CSR 7, bit 11) when STINITE (CSR 7,
bit 10) is set to 1. After generating the interrupt, the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C976 | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KIW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KCW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975VCW | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C976 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KC | 制造商:Rochester Electronics LLC 功能描述:METRIC PLASTIC QUAD-RING - Bulk |
| AM79C976KCW | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C976KD | 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。