參數(shù)資料
型號(hào)： AM79C973KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 185/304頁(yè)
文件大?。?/td> 2092K
代理商： AM79C973KCW
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Am79C973/Am79C975
185
P R E L I M I N A R Y
The STVAL value is interpreted
as an unsigned number with a
resolution of 256 Time Base
Clock periods. For instance, a
value of 122 ms would be pro-
grammed with a value of 9531
(253Bh) if the Time Base Clock is
running at 20 MHz. A value of 0 is
undefined and will result in erratic
behavior.
Read and write accessible al-
ways. STVAL is set to FFFFh af-
ter H_RESET and is unaffected
by S_RESET and the STOP bit.
BCR32: PHY Control and Status Register
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
ANTST
Reserved
tests. Written as 0 and read as
undefined.
for
manufacturing
Note
: Use of this bit will cause
data corruption and erroneous
operation.
Read/Write accessible always.
ANTST is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
14
MIIPD
MII PHY Detect. MIIPD reflects
the quiescent state of the MDIO
pin. MIIPD is continuously updat-
ed whenever there is no manage-
ment operation in progress on the
MII interface. When a manage-
ment operation begins on the in-
terface, the state of MIIPD is
preserved until the operation
ends, when the quiescent state is
again monitored and continuous-
ly updates the MIIPD bit. When
the MDIO pin is at a quiescent
LOW state, MIIPD is cleared to 0.
When the MDIO pin is at a quies-
cent HIGH state, MIIPD is set to
1. MIIPD is used by the automatic
port selection logic to select the
MII port. When the MIIPD bit is
set to 1, the MII port is selected.
Any transition on the MIIPD bit
will set the MIIPDTI bit in CSR7,
bit 3.
Read accessible always. MIIPD
is read only. Write operations are
ignored and should not be per-
formed.
13-12 FMDC
Fast Management Data Clock (is
used for manufacturing tests).
When FMDC is set to 2h the MII
Management Data Clock will run
at 10 MHz max. The Manage-
ment Data Clock will no longer be
IEEE 802.3u-compliant and set-
ting this bit should be used with
care. The accompanying external
PHY must also be able to accept
management frames at the new
clock rate. When FMDC is set to
1h, the MII Management Data
Clock will run at 5 MHz max. The
Management Data Clock will no
longer be IEEE 802.3u-compliant
and setting this bit should be
used with care. The accompany-
ing external PHY must also be
able to accept management
frames at the new clock rate.
When FMDC is set to 0h, the MII
Management Data Clock will run
at 2.5 MHz max and will be fully
compliant to IEEE 802.3u stan-
dards. See Table 37.
Read/Write accessible always.
FMDC is set to 0 during
H_RESET, and is unaffected by
S_RESET and the STOP bit
11
APEP
Auto-Poll PHY. APEP when set to
1
the
Am79C973/Am79C975
controller will poll the status regis-
ter in the PHY. This feature al-
lows the software driver or upper
layers to see any changes in the
status of the PHY. An interrupt
when enabled is generated when
the contents of the new status is
different from the previous status.
Table 37. FMDC Values
Fast Management Data Clock
2.5 MHz max
5 MHz max
10 MHz max
Reserved
FMDC
00
01
10
11
相關(guān)PDF資料
PDF描述
AM79C975KCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C973VCW PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C973VCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C974 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems
AM79C974KC 制造商:Advanced Micro Devices 功能描述:
AM79C974KC/W 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LAN Node Controller
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