參數(shù)資料
型號(hào)： AM79C972BVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 97/130頁(yè)
文件大小： 1580K
代理商： AM79C972BVCW
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Am79C972
97
PCnet-PCI II (Am79C970A) and PCnet-
FAST
(Am79C971) devices.
The PCI Device ID register is located at offset 02h in
the PCI Configuration Space. It is read only.
PCI Command Register
Offset 04h
The PCI Command register is a 16-bit register used to
control the gross functionality of the Am79C972 con-
troller. It controls the Am79C972 controller
’
s ability to
generate and respond to PCI bus cycles. To logically
disconnect the Am79C972 device from all PCI bus cy-
cles except configuration cycles, a value of 0 should be
written to this register.
The PCI Command register is located at offset 04h in
the PCI Configuration Space. It is read and written by
the host.
Bit
Name
Description
15-10
RES
Reserved locations. Read as ze-
ros; write operations have no ef-
fect.
9
FBTBEN
Fast Back-to-Back Enable. Read
as zero; write operations have no
effect. The Am79C972 controller
will not generate Fast Back-to-
Back cycles.
8
SERREN
SERR Enable. Controls the as-
sertion of the SERR pin. SERR is
disabled
when
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
SERREN
is
SERREN
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
is
cleared
by
7
RES
Reserved location. Read as ze-
ros; write operations have no ef-
fect.
6
PERREN
Parity Error Response Enable.
Enables the parity error response
functions. When PERREN is 0
and the Am79C972 controller de-
tects a parity error, it only sets the
Detected Parity Error bit in the
PCI Status register. When PER-
REN is 1, the Am79C972 control-
ler
asserts
PERR
detection of a data parity error. It
on
the
also sets the DATAPERR bit (PCI
Status register, bit 8), when the
data parity error occurred during
a master cycle. PERREN also
enables reporting address parity
errors through the SERR pin and
the SERR bit in the PCI Status
register.
PERREN
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
is
cleared
by
5
VGASNOOP
VGA Palette Snoop. Read as ze-
ro; write operations have no ef-
fect.
4
MWIEN
Memory Write and Invalidate Cy-
cle Enable. Read as zero; write
operations have no effect. The
Am79C972 controller only gener-
ates Memory Write cycles.
3
SCYCEN
Special Cycle Enable. Read as
zero; write operations have no ef-
fect. The Am79C972 controller
ignores all Special Cycle opera-
tions.
2
BMEN
Bus Master Enable. Setting
BMEN enables the Am79C972
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
Am79C972 controller.
BMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
1
MEMEN
Memory Space Access Enable.
The Am79C972 controller will ig-
nore all memory accesses when
MEMEN is cleared. The host
must set MEMEN before the first
memory access to the device.
For memory mapped I/O, the
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI Expansion ROM Base Ad-
dress register at offset 30h with a
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