參數(shù)資料
型號(hào)： AM79C972BKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 128/130頁(yè)
文件大?。?/td> 1580K
代理商： AM79C972BKCW
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128
Am79C972
ment of the desired interval,
where each bit of RXPOLLINT
approximately represents one
clock
time
period.
LINT[3:0] are ignored. (RXPOL-
LINT[16] is implied to be a 1, so
RXPOLLINT[15] is significant
and does not represent the sign
of the two
’
s complement RXPOL-
LINT value.)
RXPOL-
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
(1.966
CLK = 33 MHz). The RXPOL-
LINT value of 0000h is created
during the microcode initialization
routine and, therefore, might not
be seen when reading CSR49 af-
ter H_RESET or S_RESET.
ms
when
If the user desires to program a
value for RXPOLLINT other than
the default, then the correct pro-
cedure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR49 and then set STRT in
CSR0. In this way, the default
value of 0000h in CSR47 will be
overwritten with the desired user
value.
If the user does
not
use the stan-
dard
initialization
(standard implies use of an initial-
ization block in memory and set-
ting the INIT bit of CSR0), but
instead, chooses to write directly
to each of the registers that are
involved in the INIT operation,
then it is imperative that the user
also writes all zeros to CSR49 as
part of the alternative initialization
sequence.
procedure
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR58: Software Style
This register is an alias of the location BCR20. Accesses
to and from this register are equivalent to accesses to
BCR20.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-11 RES
Reserved locations. Written as
zeros and read as undefined.
10
APERREN
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C972
controller to use 32-bit software
structures.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C972 controller is the
target of the transfer.
Read anytime, write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
9
RES
Reserved locations. Written as
zeros and read as undefined.
8
SSIZE32
Software Size 32 bits. When set,
this
bit
indicates
Am79C972 controller utilizes 32-
bit software structures for the ini-
tialization block and the transmit
and receive descriptor entries.
When cleared, this bit indicates
that the Am79C972 controller uti-
lizes 16-bit software structures for
the initialization block and the
transmit and receive descriptor
entries.
In
this
Am79C972 controller is back-
wards
compatible
that
the
mode,
the
with
the
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