參數(shù)資料
型號(hào): AM79C971
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述: PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器,PCI總線
文件頁(yè)數(shù): 124/265頁(yè)
文件大?。?/td> 3190K
代理商: AM79C971
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124
Am79C971
9
SLPINT
Sleep Interrupt is set by the
Am79C971 controller when it
comes out of sleep mode.
When SLPINT is set, INTA is as-
serted if the enable bit SLPINTE
is 1. Note that the assertion of an
interrupt due to SLPINT is not de-
pendent on the state of the INEA
bit, since INEA is cleared by the
S_RESET reset generated when
entering the sleep mode.
Read/Write accessible always.
SLPINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. SLPINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
8
SLPINTE
Sleep
SLPINTE is set, the SLPINT bit
will be able to set the INTR bit.
Interrupt
Enable.
If
Read/Write accessible always.
SLPINTE is set to 0 by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
7
EXDINT
Excessive Deferral Interrupt is
set by the Am79C971 controller
when the transmitter has experi-
enced Excessive Deferral on a
transmit frame, where Excessive
Deferral is defined in the ISO
8802-3 (IEEE/ANSI 802.3) stan-
dard.
When EXDINT is set, INTA is as-
serted if the enable bit EXDINTE
is 1.
Read/Write accessible always.
EXDINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. EXDINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
6
EXDINTE
Excessive Deferral Interrupt En-
able. If EXDINTE is set, the
EXDINT bit will be able to set the
INTR bit.
Read/Write accessible always.
EXDINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
MPPLBA
Magic Packet Physical Logical
Broadcast Accept. If MPPLBA is
at its default value of 0, the
Am79C971 controller will only de-
tect a Magic Packet frame if the
destination address of the packet
matches the content of the physi-
cal address register (PADR). If
MPPLBA is set to 1, the destina-
tion address of the Magic Packet
frame can be unicast, multicast,
or broadcast. Note that the set-
ting of MPPLBA only affects the
address detection of the Magic
Packet frame. The Magic Packet
frame
s data sequence must be
made up of 16 consecutive phys-
ical addresses (PADR[47:0]) re-
gardless
of
what
destination address it has.
kind
of
Read/Write accessible always.
MPPLBA is set to 0 by H_RESET
or S_RESET and is not affected
by setting the STOP bit.
4
MPINT
Magic Packet Interrupt. Magic
Packet Interrupt is set by the
Am79C971 controller when the
device is in the Magic Packet
mode and the Am79C971 con-
troller receives a Magic Packet
frame. When MPINT is set to 1,
INTA is asserted if IENA (CSR0,
bit 6) and the enable bit MPINTE
are set to 1.
Read/Write accessible always.
MPINT is cleared by the host by
writing a 1. Writing a 0 has no af-
fect. MPINT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
3
MPINTE
Magic Packet Interrupt Enable. If
MPINTE is set to 1, the MPINT bit
will be able to set the INTR bit.
Read/Write accessible always.
MPINT is cleared to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
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