參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 102/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970A
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AMD
P R E L I M I N A R Y
102
Am79C970A
terminate all network activity in an orderly sequence be-
fore issuing an S_RESET.
STOP
A STOP reset is generated by the assertion of the STOP
bit in CSR0. Writing a ONE to the STOP bit of CSR0,
when the stop bit currently has a value of ZERO, will in-
itiate a STOP reset. If the STOP bit is already a ONE,
then writing a ONE to the STOP bit will not generate a
STOP reset.
STOP will reset all or some portions of CSR0, 3, and 4 to
default values. For the identity of individual CSRs and bit
locations that are affected by STOP, see the individual
CSR register descriptions. STOP will not affect any of
the BCR and PCI configuration space locations. STOP
will cause the microcode program to jump to its reset
state. Following the end of the STOP operation, the
PCnet-PCI II controller will not attempt to read the
EEPROM device. Setting the STOP bit does not affect
the T-MAU.
Note that STOP will not cause a deassertion of the
REQ
signal, if it happens to be active at the time of the
write to CSR0. The PCnet-PCI II controller will wait
until it gains bus ownership and it will first finish all
scheduled bus master accesses before the STOP reset
is executed.
STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to ter-
minate all network activity in an orderly sequence before
setting the STOP bit.
Software Access
PCI Configuration Registers
The PCnet-PCI II controller implements a 256-byte con-
figuration space as defined by the PCI specification
revision 2.0. The 64-byte header includes all registers
required to identify the PCnet-PCI II controller and its
function. Additional registers are used to setup the con-
figuration of the PCnet-PCI II controller in a system.
None of the device specific registers located at offsets
40h through FCh are implemented. The layout of the
PCnet-PCI II controller PCI configuration space is
shown in the table below.
The PCI configuration registers are accessible only by
configuration cycles. All multi-byte numeric fields follow
little endian byte ordering. All write accesses to Re-
served locations have no effect; reads from these loca-
tions will return a data value of ZERO.
Table 18. PCI Configuration Space Layout
Device ID
Status
Vendor ID
Command
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
.
Base-Class
Reserved
Sub-Class
Header Type
Programming IF
Latency Timer
Revision ID
Reserved
I/O Base Address
Memory Mapped I/O Base Address
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Expansion ROM Base Address
Reserved
Reserved
MIN_GNT
Reserved
Reserved
Reserved
MAX_LAT
Interrupt Pin
Interrupt Line
FCh
31
24 23
16
15
8
7
0
Offset
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
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AM79C970AKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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