參數(shù)資料
型號： AM79C930
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
中文描述： PCnet -移動單芯片無線局域網(wǎng)媒體接入控制器
文件頁數(shù)： 38/161頁
文件大?。?/td> 691K
代理商： AM79C930
AMD
P R E L I M I N A R Y
38
Am79C930
Pin 101: SDCLK
The SDCLK pin may be configured for input or output
operation. The output drive may be programmed for reg-
ister-driven or auto-pulse generation. The auto-pulse
may be programmed for either active low or active high
operation. SDCLK pin configuration is accomplished ac-
cording to the following table:
Note that a read of the SDC bit (TIR2[2]) will always
give the current SDCLK pin value, regardless of pin
configuration setting.
SDCLKEN
TCR13[4]
0
1
1
1
1
SDCP
TIR2[3]
X
0
1
0
1
SDC
TIR2[2]
X
0
0
1
1
SDCLK Pin
Direction
I
O
O
O
O
SDCLK Pin
Value
NA
LOW
HIGH active pulse
HIGH
LOW active pulse
reset default condition
(when write to TIR2 occurs)
(when write to TIR2 occurs)
Pin 102: SDDATA
The SDDATA pin may be configured for input or output
operation. SDDATA pin configuration is accomplished
according to the following table:
Note that a read of the SDD bit (TIR2[0]) will always
give the current SDDATA pin value, regardless of pin
configuration setting.
SDDT
TIR2[1]
0
0
1
SDD
TIR2[0]
0
1
X
SDDATA Pin
Direction
O
O
I
SDDATA Pin
Value
LOW
HIGH
NA
reset default condition
Pin 103:
SDSEL3
The
SDSEL
[
3
] pin may be configured for input or output
operation according to the following table:
Note that a read of the SDS[3] bit (TIR2[6]) will always
give the current
SDSEL
[
3
] pin value without inversion,
regardless of pin configuration setting.
SDSEL3
EN
TCR13[3]
0
1
1
SDS[
3
]
TIR2[6]
X
0
1
SDSEL
[
3
]
Pin Direction
I
O
O
SDSEL
[
3
]
Pin Value
NA
HIGH
LOW
reset default condition
Pin 105:
SDSEL2
The
SDSEL
[
2
] pin may be configured for input or output
operation according to the following table:
Note that a read of the SDS[2] bit (TIR2[5]) will always
give the current
SDSEL
[
2
] pin value without inversion,
regardless of pin configuration setting.
SDSEL2
EN
TCR13[2]
0
1
1
SDS[
2
]
TIR2[5]
X
0
1
SDSEL
[
2
]
Pin Direction
I
O
O
SDSEL
[
2
]
Pin Value
NA
HIGH
LOW
reset default condition
Pin 107:
SDSEL1
The
SDSEL
[
1
] pin may be configured for input or output
operation according to the following table:
Note that a read of the SDS[1] bit (TIR2[4]) will always
give the current
SDSEL
[
1
] pin value without inversion,
regardless of pin configuration setting.
SDSEL1
EN
TCR13[1]
0
1
1
SDS[1]
TIR2[4]
X
0
1
SDSEL
[1]
Pin Direction
I
O
O
SDSEL
[1]
Pin Value
NA
HIGH
LOW
reset default condition
相關(guān)PDF資料
PDF描述
AM79C930VCW PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
AM79C940VCW Media Access Controller for Ethernet (MACE)
AM79C940 Media Access Controller for Ethernet (MACE)
AM79C940JCW Media Access Controller for Ethernet (MACE)
AM79C940KCW Media Access Controller for Ethernet (MACE)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C930EVAL-HW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C930EVAL-HW - PCnet-Mobile Evaluation Kit
AM79C930VC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
AM79C930VCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
AM79C940 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE)
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