參數(shù)資料
型號(hào)： AM79C874VC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP80
封裝： 12 X 12 MM, PLASTIC, MO-136BAM, TQFP-80
文件頁數(shù)： 21/60頁
文件大?。?/td> 869K
代理商： AM79C874VC
Am79C874
21
P R E L I M I N A R Y
Figure 3.
TX± and RX± Termination for 100BASE-TX and 10BASE-T
Clock/Data Recovery
The equalized MLT-3 signal passes through a slicer cir-
cuit which then converts it to NRZI format. The Net-
PHY-1LP device uses an analog phase-locked loop
(APLL) to extract clock information from the incoming
NRZI data. The extracted clock is used to re-time the
data stream and set the data boundaries. The transmit
clock is locked to the 25-MHz clock input, while the re-
ceive clock is locked to the incoming data streams.
When initial lock is achieved, the APLL switches to lock
to the data stream, extracts a 125 MHz clock from it and
use that for bit framing to recover data. The recovered
125 MHz clock is also used to generate the 25 MHz
RX_CLK. The APLL requires no external components
for its operation and has high noise immunity and low
jitter. It provides fast phase align (lock) to data in one
transition and its data/clock acquisition time after
power-on is less than 60 transitions.
The APLL can maintain lock on run-lengths of up to 60
data bits in the absence of signal transitions. When no
valid data is present, i.e., when the SD is de-asserted,
the APLL switches back to lock with TX_CLK, thus pro-
viding a continuously running RX_CLK.
The recovered data is converted from NRZI-to-NRZ
and then to a 5-bit parallel format. The 5-bit parallel
data is not necessarily aligned to 4B/5B code-group
’
s
symbol boundary. The data is presented to PCS at re-
ceive data register output, gated by the 25-MHz
RX_CLK.
PLL Clock Synthesizer
The NetPHY-1LP device includes an on-chip PLL clock
synthesizer that generates a 125 MHz and a 25 MHz
clock for the 100BASE-TX or a 100 MHz and 20 MHz
clock for the 10BASE-T and Auto-Negotiation opera-
tions. Only one external 25 MHz crystal or a signal
source is required as a reference clock.
After power-on or reset, the PLL clock synthesizer is
defaulted to generating the 20 MHz clock output and
will stay active until the 100BASE-X operation mode is
selected.
RX+
TX+
RX-
TX-
0.1
μ
F
0.1
μ
F
V
DD
(Note 1)
(Note 1)
470 pF, 2 kV
(chassis ground)
(8)
(7)
TX+ (1)
(5)
(4)
TX- (2)
RX+ (3)
RX- (6)
75
75
75
75
Isolation
Transformer with
common-mode
chokes
RJ45
Connector
1:1 or 1.25:1
1:1
0.1
μ
F
(Note 2)
(Note 2)
22235I-5
Notes:
1. 49.9
if a 1:1 isolation transformer is used or 78.1
if a 1.25:1 isolation transformer is used.
2. 49.9
is normal, but 54.9
can be used for extended cable length operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C874VD 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874VF 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874VI 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP 制造商:AMD (Advanced Micro Devices) 功能描述:PHY 1-CH 10Mbps/100Mbps 80-Pin TQFP
AM79C874WW 制造商:Advanced Micro Devices 功能描述:8" WAFER, DIE IN WAFER FORM, SINGLE PORT ETHERNET 10/100 - Trays
AM79C875 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:NetPHY⑩ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver
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