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參數(shù)資料
| 型號： | AM7992 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Interface Adapter (SIA) |
| 中文描述： | 串行接口適配器（新航） |
| 文件頁數(shù)： | 15/27頁 |
| 文件大小： | 224K |
| 代理商： | AM7992 |
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AMD
1
5
Am7992B
SWITCHING CHARACTERISTICS (continued)
*Min = 4.5 V, Max = 5.5 V, T
OSC
= 50 ns; in production test, all differential input test conditions are done single-ended,
non-V
IRD
levels are forces on DUT for waveform swing (levels chosen are due to tester limitations) and a distortion-free
preamble is applied to Receive
±
inputs.
Notes:
1. Tested but to values in excess of limits. Test accuracy not sufficient to allow screening guardbands.
2. Correlated to other tested parameter: I
OD
OFF = V
OD
OFF/R
L
.
3. Not tested.
4. Test done by monitoring output functionally.
5. Receive, Collision and Transmit functions are inactive: X1 driven by 20 MHz.
6. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
7. TCLK changes state on X1 rising edge, but initial state of TCLK is not defined. When TENA is High, TX data is
Manchester encoded on the falling edge of X1 after the rising edge of TCLK.
8. Assumes 50 pF capacitance loading on RCLK and RX.
9. Test is done only for last BIT = 1, which is worst case.
10. Test done from 0.8 V of falling to 2.0 V of rising edge.
11. Test correlated to T
TCH
.
12. Measured from 50% point of X1 driving the input in production test.
No.
Transmitter Specification
Parameters
Description
Test Conditions
Min
Max
Unit
24
t
TCL
TCLK LOW Time
(Note 11)
45
ns
25
t
TCH
TCLK HIGH Time
45
ns
26
t
TCR
TCLK Rise Time
8
ns
27
t
TCF
TCLK Rise Time
8
ns
28
t
TDS
, t
TES
TX and TENA Setup Time to TCLK
5
ns
29
t
TDH
, t
TEH
TX and TENA Hold Time to TCLK
Transmit
±
Output, (Bit Cell Center to Edge)
TCLK HIGH to Transmit
±
Output
Transmit
±
Output Rise Time
Transmit
±
Output Fall Time
X1
to TCLK Propagation Delay for HIGH
5
ns
30
t
TOCE
49.5
50.5
ns
31
t
OD
100
ns
32
t
TOR
4
ns
33
t
TOF
4
ns
34
t
XTCH
5
18
ns
35
t
XTCL
X1
to TCLK Propagation Delay for LOW
5
18
ns
36
t
EJ1
Clock Acquisition Jitter Tolerance
V
CC
= 5.0 V (Note 1)
16
21.5
ns
37
t
EJ51
Jitter Tolerance After 50 Bit Times
V
CC
= 5.0 V (Note 1)
19
24.4
ns
(Note 1)
20% – 80%
(Notes 7 & 12)
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| AM7992BPCB | Serial Interface Adapter (SIA) |
| AM7992B | Serial Interface Adapter (SIA) |
| AM7992BDC | Serial Interface Adapter (SIA) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7992ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Interface |
| AM7992B | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Serial Interface Adapter (SIA) |
| AM7992B/BLA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Interface |
| AM7992BDC | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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