- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366548 > Am7969-175LKC (Advanced Micro Devices, Inc.) TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) PDF資料下載
參數(shù)資料
| 型號(hào)： | Am7969-175LKC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁(yè)數(shù)： | 15/127頁(yè) |
| 文件大?。?/td> | 730K |
| 代理商： | AM7969-175LKC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
AMD
11
Am7968/Am7969
Am7968 Encoder/Am7969 Decoder
To guarantee that the Am7969’s PLL can stay locked
onto an incoming bit stream, the data encoding scheme
must provide an adequate number of transitions in each
data pattern. This implies a limit on the maximum time
allowed between transitions. The TAXIchip set encod-
ing scheme is based on the ANSI X3T9.5 (FDDI) com-
mittee’s 4-bit/5-bit (4B/5B) code.
An ANSI X3T9.5 system used an 8-bit parallel data pat-
tern. This pattern is divided into two 4-bit nibbles which
are each encoded into a 5-bit symbol. Of the thirty-two
patterns possible with these five bits, sixteen are chosen
to represent the sixteen input Data patterns. Some of
the others are used as Command symbols. Those re-
maining represent invalid patterns that fail either the
run-length test or DC balance tests.
Transmitters in 8-bit mode use two 4B/5B encoders to
encode eight Data bits into a 10-bit pattern. In 9-bit
mode, Transmitters use one 5B/6B encoder and one
4B/5B encoder to code nine Data bits into an 11-bit pat-
tern. In 10-bit mode, two 5B/6B encoders are used to
change ten bits of Data into a 12-bit pattern (see Tables
1 and 2 for encoding patterns).
The Am7968 Transmitter further encodes all symbols
using NRZI (Non Return to Zero, Invert on Ones). NRZI
represents a “1” by a transition and a “0” by the lack of
transition. In this system a “1” can be a HIGH-to-LOW or
LOW-to-HIGH transition. This combination of 4B/5B
and NRZI encoding ensures at least two transitions per
symbol and permits a maximum of three consecutive
non-transition bit times. The Am7969 then uses the
same method to decode incoming symbols so that the
whole encoding/decoding process is transparent to
the user.
Most Serially transmitted data patterns with this code
will have the same average amount of HIGH and LOW
times. This near DC balance minimizes pattern-sensi-
tive decoding errors which are caused by jitter in AC-
coupled systems.
Operational Modes
In normal operational mode, a single Transmitter/
Receiver pair is used to transfer 8, 9, or 10 bits of parallel
Data over a private serial link. (On the Am7968, the TLS
pin is tied to ground and TSERINis left unconnected).
On the Am7969, CNBmust be connected to the CLK
output. The Am7969 Receiver continuously deserial-
izes the incoming bit stream, decodes the resulting pat-
terns, and saves parallel data at its output latches (see
Figure 3).
Local mode provides a fast and efficient parallel
throughout because data can be transferred on every
clock cycle. On the other hand, it is not necessary for the
host to match the byte rate set by the Transmitter’s crys-
tal oscillator; the Am7968 automatically sends a Sync
pattern during each clock cycle in which no new Data or
Command messages are being transmitted.
Cascade Mode (for –125 only)
For very wide parallel buses, TAXI Receiver’s (commer-
cial temperature parts only) can be Cascaded. The
Am7969 Receivers all have their SERIN+and SERIN–
pins connected to the media (or an optical data link).
IGMof each Am7969 is connected to CNBof its down-
stream neighbor or is left unconnected on the Receiver
farthest downstream. CNBof the first Receiver is tied
HIGH, making this device the only Receiver in the chain
that can act on the first non-Sync pattern in a message
(see below).
Each TAXIchip Receiver monitors the serial link and a
special acknowledgment scheme is used to direct sym-
bols into each of the Am7969s. When a Catch-Next-
Byte (CNB) input is HIGH, the Receiver will capture the
next non-Sync symbol from the serial link. At this point,
the device forces its I-Got-Mine (IGM) pin HIGH to tell
the downstream Receiver to capture the next symbol.
The Receiver then waits for the Sync symbol or for its
CNBto be set LOW before transferring the message to
its output latch. IGMis forced LOW whenever a Sync
byte is detected or when CNBgoes LOW. This IGM-
CNBexchange continues down the chain until the last
Receiver captures its respective byte. The next byte to
appear on the serial link will be a Sync symbol which is
detected by all of the cascaded Am7969s. On the follow-
ing Clock cycle their messages are transferred to the
output latch of each device and sent to the receiving
host. IGMpins on all Receivers are also set LOW when
the first half of the Sync symbol is detected.
Asynchronous Operation
Inputs to the Am7968 Transmitter Input Latch can be
asynchronous to its internal clock. Data STRBwill latch
data into the Am7968 Transmitter and an internal clock
will transfer the data to the Encoder Latch at the first
byte boundary. Data can be entered at any rate less
than the maximum transfer rate without regard to actual
byte boundaries. As data rates approach the TAXI
BYTE RATE, care must be taken to insure that the 2
BYTE FIFO inside TAXI Transmitter is not over filled.
STRB/ACKhandshake will assure that every byte is
transferred correctly. At higher byte rates, where delays
and setup/hold times make the STRB/ACKhandshake
impractical, STRBshould be synchronized with CLK
Synchronous Operation
The Transmitter may be strobed synchronous by tying
the strobe to the input clock. When doing this a provision
should be make to inhibit the strobe periodically to en-
sure proper byte alignment. In the absence of a strobe,
Syncs will be transmitted on the serial link which will al-
low the receiver to re-align the byte boundaries. In addi-
tion it is essential that the delay between the falling edge
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM7968-125VB3A | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125VB3A | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175JC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175JC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-125DC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7969-175LMC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-175PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-70/B3A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-70/BXA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。