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參數(shù)資料
| 型號： | AM7969-175JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | LINE RECEIVER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 90/127頁 |
| 文件大?。?/td> | 730K |
| 代理商： | AM7969-175JC |
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AMD
86
TAXIchip Integrated Circuits Technical Manual
the drive capability of the Transmitter and the termination circuit for multidrop transmis-
sion lines. Similarly, several Transmit bytes can be multiplexed to one Receiver. There
are no drive considerations in this case.
Figure 7-12 shows an example of an unbalanced mode of operation in which one
Transmitter is connected to three Receivers.
Figure 7-12
Unbalanc ed Configuration Example: One T ransmitter to T hree Rec eivers
TTL Data IN
SERIN
CNB
X1
IGM
8,
9,
10
Am7969
V
CC
SERIN
CNB
X1
8,
9,
10
Am7969
SERIN
CNB
X1
IGM
8,
9,
10
Am7969
+
SEROUT
–
8,
9,
10
X1
X2
Am7968
Clock
OSC
12330E-34
TTL Data OUT
Note that in the Unbalanced Configuration, attention has to be given to where a Sync
will be needed. Either the Auto-Repeat Receiver Configuration should be used or a
Sync must be provided every (R + 1) bytes, where R is the number of Receivers
cascaded together. More information on proper use and requirement of SYNC, refer to
Appendix C, TAXI TIP #8903.
8.0 T ES T MODE
The Phase Locked Loops (PLLs) in the TAXlchips are designed to run within a fre-
quency range that has been set for maximum efficiency and accuracy. The lower limit of
this frequency range is 40 MHz.
In Test Mode, the PLLs of the Transmitter and the Receiver are disconnected and the
internal clock is applied from an external source. This allows the TAXls to function at a
much slower speed. This mode was designed to simplify the testing of TAXls in an
automatic testing production environment. A by-product of Test Mode is that it allows the
user to run the TAXls in systems that are slower than 4 MHz (the minimum byte rate). In
this mode there is no minimum frequency.
A system that needs to transfer data at LOW byte data rates can normally be imple-
mented without modifying the standard setup, and Test Mode need not be used. When
there is no data to be sent, the TAXlchips will keep the line active by sending Syncs.
相關PDF資料 |
PDF描述 |
|---|---|
| AM7968-125DC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-125DMC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-125JC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-125LMC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175DC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM7969-175LKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175LMC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-175PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
| AM7969-70/B3A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
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