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| 型號(hào)： | Am7969-175DKC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁(yè)數(shù)： | 96/127頁(yè) |
| 文件大?。?/td> | 730K |
| 代理商： | AM7969-175DKC |
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AMD
92
TAXIchip Integrated Circuit Technical Manual
For example, consider transmitting Hex B[1011], encoded as 10111. Error E occurs
changes bits b0 & b1, resulting in encoded pattern 10100, which is Hex 2 [0010]
2 bits changed, and the run length the error = 4 bits,
1 0 1 1
0 0 1 0
becomes
2 bits changed, and the run length
the error = 4 bits,
A double bit error can change valid data into a Violation, a valid Command byte, a 1-bit,
2-bit, 3-bit,or 4-bit data error. A summary of the occurrence of these errors for the six
error locations for 4B/5B encoding is summarized below in Table B1.
T able B-1
Error T ype
A
B
C
D
E
F
V=5
C=5
1B=4
2B=2
3B=0
4B=0
V=5
C=3
1B=0
2B=8
3B=0
4B=0
V=5
C=5
1B=2
2B=4
3B=0
4B=0
V=3
C=3
1B=4
2B=6
3B=0
4B=0
V=3
C=5
1B=0
2B=6
3B=0
4B=2
V=1
C=1
1B=14
2B=0
3B=0
4B=0
T able B-2
Similar reasoning for the 5B/6B encoding scheme results in seven possible error
locations, and the summary of the occurrence of these errors is listed below:
A
B
C
D
E
F
G
V=13
C=3
1B=10
2B=6
3B=0
4B=0
V=16
C=2
1B=0
2B=14
3B=0
4B=0
V=12
C=2
1B=0
2B=12
3B=4
4B=2
V=6
C=4
1B=0
2B=14
3B=6
4B=2
V=9
C=3
1B=8
2B=12
3B=0
4B=0
V=10
C=4
1B=2
2B=12
3B=0
4B=4
V=5
C=3
1B=22
2B=2
3B=0
4B=0
Utilizing this information one can determine the efficiency of the violation logic in the
TAXI Receiver. Figure B2 summarizes the violation effectiveness, as well as depicting
the number of bits in error in the undetected corrupted data. This information can be
extremely useful in determining what, if any, additional error detection schemes should
be implemented. Figure B3 graphically represents the run length of the corrupted data
for the undetected errors. As shown in this figure, there are a small percentage of
unlimited run length errors. This is due to the few data patterns, which, when corrupted
will cause a false Sync pattern to be generated. This pattern will cause a running error
which will continue until the next valid Sync realigns the byte edge to its proper position.
While these false Syncsoccur very rarely, these are the most dangerous errors in a
TAXI system, this very well may dictate the maximum user packetsize.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am7969-125 | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125DC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125DMC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-125JC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125LMC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7969-175DMC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175JC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175LKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175LMC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7969-175PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Receiver |
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