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參數(shù)資料
| 型號： | AM75PDL193CHH70I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | FBGA-73 |
| 文件頁數(shù)： | 21/136頁 |
| 文件大?。?/td> | 1250K |
| 代理商： | AM75PDL193CHH70I |
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February 5, 2004
Am75PDL191CHH/Am75PDL193CHH
19
A D V A N C E I N F O R M A T I O N
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the OE# and appropriate CE#f1/CE#f2 (PDL129
only) pins to V
IL
. CE#f1 and CE#f2 are the power con-
trol and for PDL129 select the lower (CE#f1) or upper
(CE#f2) halves of the device. OE# is the output control
and gates array data to the output pins. WE# should
remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Characteristics table for timing specifi-
cations and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Random Read (Non-Page Read)
Address access time (t
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable ad-
dresses and stable CE#f1 to valid data at the output
inputs. The output enable access time is the delay
from the falling edge of the OE# to valid data at the
output inputs (assuming the addresses have been sta-
ble for at least t
ACC
–t
OE
time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. Address bits
A22–A3 (A21–A3 for PDL129) select an 8-word page,
and address bits A2–A0 select a specific word within
that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
The random or initial page access is t
ACC
or t
CE
and
subsequent page read accesses (as long as the loca-
tions specified by the microprocessor fall within that
page) are t
PACC
. When CE#f1 and CE#f2 (PDL129
only) are deasserted (CE#f1=CE#f2=V
IH
), the reasser-
tion of CE#f1 or CE#f2 (PDL129 only) for subsequent
access has access time of t
ACC
or t
CE
. Here again,
CE#f1/CE#f2 (PDL129 only) selects the device and
OE# is the output control and should be used to gate
data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping
A22–A3 (A21–A3 for PDL129) constant and changing
A2 to A0 to select the specific word within that page.
Table 2.
Page Select
Simultaneous Operation
In addition to the conventional features (read, pro-
gram, erase-suspend read, and erase-suspend pro-
gram), the device is capable of reading data from one
bank of memory while a program or erase operation is
in progress in another bank of memory (simultaneous
operation), The bank can be selected by bank ad-
dresses (A22–A20) (A21–A20 for PDL129) with zero
latency.
The simultaneous operation can execute multi-func-
tion mode in the same bank.
Table 3.
Bank Select (PDL129H)
Table 4.
Bank Select (PDL127H)
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Bank
CE#f1
CE#f2
A21–A20
Bank 1A
0
1
00, 01, 10
Bank 1B
0
1
11
Bank 2A
1
0
00
Bank 2B
1
0
01, 10, 11
Bank
A22–A20
Bank A
000
Bank B
001, 010, 011
Bank C
100, 101, 110
Bank D
111
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