參數(shù)資料
型號： AM75DL9608HGB70IT
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： 64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 8 X 11.60 MM, FBGA-73
文件頁數(shù)： 15/70頁
文件大小： 575K
代理商： AM75DL9608HGB70IT
November 17, 2003
Am75DL9608HG
13
A D V A N C E I N F O R M A T I O N
vice requires standard access time (t
CE
) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
f in the table represents the standby current speci-
fication.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5
f in the table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
f). If RESET# is
held at V
IL
but not within V
SS
±0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embedded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
Refer to the Flash AC Characteristics tables for RE-
SET# parameters and to Figure 15 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
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AM75DL9608HGB75IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
AM75DL9608HGB75IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
AM75DL9608HGT70IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
AM75DL9608HGT70IT 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
AM75DL9608HGT75IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
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