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參數(shù)資料
| 型號(hào)： | AM70PDL127CDH66IS |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 13 X 9 MM, FBGA-93 |
| 文件頁(yè)數(shù)： | 124/127頁(yè) |
| 文件大小： | 846K |
| 代理商： | AM70PDL127CDH66IS |
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122
Am70PDL127CDH/Am70PDL129CDH
November 24, 2003
A D V A N C E I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
. Programming specifications assume that
all bits are programmed to 00h.
2. Maximum values are measured at V
CC
= 3.0 V worst case temperature. Maximum values are valid up to and including 100,000
program/erase cycles.
3. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
4. For 1-16 words programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables
12
and
11
for further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Note:
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.5
15
sec
Chip Erase Time
32
128
sec
Single Word Program Time (Note 3)
Word
100
TBD
μs
Accelerated Single Word Program Time
(Note 3)
Word
90
TBD
μs
Total Write Buffer Program Time (Note 4)
352
TBD
μs
Effective Write Buffer Program Time (Note 3) Per Word
22
TBD
μs
Total Accelerated Effective Write Buffer
Program Time (Note 4)
282
TBD
μs
Effective Accelerated Write Buffer PRogram
Time (Note 4)
Word
17.6
TBD
μs
Chip Program Time
92
TBD
sec
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
V
CC
Current
–1.0 V
V
CC
+ 1.0 V
+100 mA
–100 mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM70PDL127CDH66IT | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85I | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IS | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IT | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL129CDH | Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM70PDL127CDH66IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL129BDH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
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