參數(shù)資料
型號(hào)： AM70PDL127BDH66I
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
中文描述： 堆疊式多芯片封裝（MCP / XIP）的快閃記憶體，數(shù)據(jù)存儲(chǔ)的MirrorBit閃存和移動(dòng)存儲(chǔ)芯片（XIP）的
文件頁(yè)數(shù)： 8/128頁(yè)
文件大?。?/td> 916K
代理商： AM70PDL127BDH66I
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6
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
A D V A N C E I N F O R M A T I O N
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. Test Setup, VIO = 2.7 – 3.3 V....................................... 61
Figure 11. Input Waveforms and Measurement Levels .................. 61
Hardware Reset (RESET#) ....................................................62
Figure 12. Reset Timings................................................................ 62
Erase and Program Operations ..............................................63
Figure 13. Program Operation Timings........................................... 64
Figure 14. Accelerated Program Timing Diagram........................... 64
Figure 15. Chip/Sector Erase Operation Timings ........................... 65
Figure 16. Back-to-back Read/Write Cycle Timings ....................... 66
Figure 17. Data# Polling Timings (During Embedded Algorithms).. 66
Figure 18. Toggle Bit Timings (During Embedded Algorithms)....... 67
Figure 19. DQ2 vs. DQ6.................................................................. 67
Temporary Sector Unprotect ..................................................68
Figure 20. Temporary Sector Unprotect Timing Diagram............... 68
Figure 21. Sector/Sector Block Protect and
Unprotect Timing Diagram.............................................................. 69
Alternate CE#f1 Controlled Erase and Program Operations ..70
Figure 22. Flash Alternate CE#f1 Controlled Write (Erase/Program)
Operation Timings........................................................................... 71
Read Cycle .............................................................................72
Figure 23. Psuedo SRAM Read Cycle............................................ 72
Figure 24. Page Read Timing......................................................... 73
Write Cycle .............................................................................74
Figure 25. Pseudo SRAM Write Cycle—WE# Control.................... 74
Figure 26. Pseudo SRAM Write Cycle—CE#1ps Control............... 75
Figure 27. Pseudo SRAM Write Cycle—
UB#s and LB#s Control................................................................... 76
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . .77
pSRAM Power on and Deep Power Down . . . . . 77
Figure 28. Deep Power-down Timing.............................................. 77
Figure 29. Power-on Timing............................................................ 77
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . .78
Figure 30. Read Address Skew ...................................................... 78
Figure 31. Write Address Skew....................................................... 78
Erase And Programming Performance . . . . . . . . 79
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 79
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 79
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 79
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .81
Table 1. Device Bus Operations .....................................................81
VersatileIO
(V
IO
) Control .....................................................81
Requirements for Reading Array Data ...................................81
Page Mode Read ................................................................82
Writing Commands/Command Sequences ............................82
Write Buffer .........................................................................82
Accelerated Program Operation ..........................................82
Autoselect Functions ...........................................................82
Standby Mode ........................................................................ 82
Automatic Sleep Mode ...........................................................83
RESET#: Hardware Reset Pin ...............................................83
Output Disable Mode ..............................................................83
Table 2. Sector Address Table ........................................................84
Sector Group Protection and Unprotection .............................87
Table 3. Sector Group Protection/Unprotection Address Table .....87
Write Protect (WP#) ................................................................ 88
Temporary Sector Group Unprotect .......................................88
Figure 1. Temporary Sector Group Unprotect Operation................ 88
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 89
SecSi (Secured Silicon) Sector Flash Memory Region ..........90
Table 4. SecSi Sector Contents ..................................................... 90
Figure 3. SecSi Sector Protect Verify............................................. 90
Hardware Data Protection ......................................................91
Low VCC Write Inhibit .........................................................91
Write Pulse “Glitch” Protection ............................................91
Logical Inhibit .......................................................................91
Power-Up Write Inhibit .........................................................91
Common Flash Memory Interface (CFI) . . . . . . . 91
Table 5. CFI Query Identification String.......................................... 91
System Interface String................................................................... 92
Table 7. Device Geometry Definition .............................................. 92
Table 8. Primary Vendor-Specific Extended Query ........................ 93
Command Definitions. . . . . . . . . . . . . . . . . . . . . . 93
Reading Array Data ................................................................93
Reset Command .....................................................................94
Autoselect Command Sequence ............................................94
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..94
Word Program Command Sequence ......................................94
Unlock Bypass Command Sequence ..................................95
Write Buffer Programming ...................................................95
Accelerated Program ...........................................................96
Figure 4. Write Buffer Programming Operation.............................. 97
Figure 5. Program Operation ......................................................... 98
Program Suspend/Program Resume Command Sequence ...98
Figure 6. Program Suspend/Program Resume.............................. 99
Chip Erase Command Sequence ...........................................99
Sector Erase Command Sequence ........................................99
Figure 7. Erase Operation............................................................ 100
Erase Suspend/Erase Resume Commands .........................100
Command Definitions ........................................................... 101
Command Definitions (x16 Mode)................................................. 101
Write Operation Status . . . . . . . . . . . . . . . . . . . 102
DQ7: Data# Polling ...............................................................102
Figure 8. Data# Polling Algorithm ................................................ 102
RY/BY#: Ready/Busy# .......................................................... 103
DQ6: Toggle Bit I ..................................................................103
Figure 9. Toggle Bit Algorithm...................................................... 104
DQ2: Toggle Bit II .................................................................104
Reading Toggle Bits DQ6/DQ2 .............................................104
DQ5: Exceeded Timing Limits ..............................................105
DQ3: Sector Erase Timer .....................................................105
DQ1: Write-to-Buffer Abort ...................................................105
Table 10. Write Operation Status ................................................. 105
Absolute Maximum Ratings . . . . . . . . . . . . . . . 106
Figure 10. Maximum Negative Overshoot Waveform.................. 106
Figure 11. Maximum Positive Overshoot Waveform.................... 106
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . 106
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 107
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 12. Test Setup................................................................... 108
Table 11. Test Specifications ....................................................... 108
Key to Switching Waveforms. . . . . . . . . . . . . . . 108
Figure 13. Input Waveforms and
Measurement Levels.................................................................... 108
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 109
Read-Only Operations ..........................................................109
Figure 14. Read Operation Timings............................................. 109
Figure 15. Page Read Timings .................................................... 110
Hardware Reset (RESET#) ..................................................111
Figure 16. Reset Timings............................................................. 111
相關(guān)PDF資料
PDF描述
AM70PDL127BDH85I Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL129BDH66I Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL129BDH85I Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL7BDH66IS Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL7BDH66IT Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM70PDL127BDH66IS 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
AM70PDL127BDH66IT 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
AM70PDL127BDH85I 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
AM70PDL127BDH85IS 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
AM70PDL127BDH85IT 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
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